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GeorgeCGVkartben
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drivers: memc: stm32: FMC NOR/PSRAM refactor
Simplifies the driver code: * Use existing FMC_NORSRAM_DEVICE and FMC_NORSRAM_EXTENDED_DEVICE defines. No need to keep references to them in the driver's config. * Refine initialization loop. Signed-off-by: Georgij Černyšiov <[email protected]>
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drivers/memc/memc_stm32_nor_psram.c

Lines changed: 21 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -6,18 +6,11 @@
66

77
#define DT_DRV_COMPAT st_stm32_fmc_nor_psram
88

9-
#include <zephyr/device.h>
109
#include <soc.h>
11-
#include <errno.h>
12-
10+
#include <zephyr/device.h>
1311
#include <zephyr/logging/log.h>
1412
LOG_MODULE_REGISTER(memc_stm32_nor_psram, CONFIG_MEMC_LOG_LEVEL);
1513

16-
/** SRAM base register offset, see FMC_Bank1_R_BASE */
17-
#define SRAM_OFFSET 0x0000UL
18-
/** SRAM extended mode register offset, see FMC_Bank1E_R_BASE */
19-
#define SRAM_EXT_OFFSET 0x0104UL
20-
2114
/** FMC NOR/PSRAM controller bank configuration fields. */
2215
struct memc_stm32_nor_psram_bank_config {
2316
FMC_NORSRAM_InitTypeDef init;
@@ -27,8 +20,6 @@ struct memc_stm32_nor_psram_bank_config {
2720

2821
/** FMC NOR/PSRAM controller configuration fields. */
2922
struct memc_stm32_nor_psram_config {
30-
FMC_NORSRAM_TypeDef *nor_psram;
31-
FMC_NORSRAM_EXTENDED_TypeDef *extended;
3223
const struct memc_stm32_nor_psram_bank_config *banks;
3324
size_t banks_len;
3425
};
@@ -37,12 +28,11 @@ static int memc_stm32_nor_init(const struct memc_stm32_nor_psram_config *config,
3728
const struct memc_stm32_nor_psram_bank_config *bank_config)
3829
{
3930
FMC_NORSRAM_TimingTypeDef *ext_timing;
40-
NOR_HandleTypeDef hnor = { 0 };
41-
42-
hnor.Instance = config->nor_psram;
43-
hnor.Extended = config->extended;
44-
45-
memcpy(&hnor.Init, &bank_config->init, sizeof(hnor.Init));
31+
NOR_HandleTypeDef hnor = {
32+
.Instance = FMC_NORSRAM_DEVICE,
33+
.Extended = FMC_NORSRAM_EXTENDED_DEVICE,
34+
.Init = bank_config->init
35+
};
4636

4737
if (bank_config->init.ExtendedMode == FMC_EXTENDED_MODE_ENABLE) {
4838
ext_timing = (FMC_NORSRAM_TimingTypeDef *)&bank_config->timing_ext;
@@ -63,12 +53,11 @@ static int memc_stm32_psram_init(const struct memc_stm32_nor_psram_config *confi
6353
const struct memc_stm32_nor_psram_bank_config *bank_config)
6454
{
6555
FMC_NORSRAM_TimingTypeDef *ext_timing;
66-
SRAM_HandleTypeDef hsram = { 0 };
67-
68-
hsram.Instance = config->nor_psram;
69-
hsram.Extended = config->extended;
70-
71-
memcpy(&hsram.Init, &bank_config->init, sizeof(hsram.Init));
56+
SRAM_HandleTypeDef hsram = {
57+
.Instance = FMC_NORSRAM_DEVICE,
58+
.Extended = FMC_NORSRAM_EXTENDED_DEVICE,
59+
.Init = bank_config->init
60+
};
7261

7362
if (bank_config->init.ExtendedMode == FMC_EXTENDED_MODE_ENABLE) {
7463
ext_timing = (FMC_NORSRAM_TimingTypeDef *)&bank_config->timing_ext;
@@ -88,21 +77,21 @@ static int memc_stm32_psram_init(const struct memc_stm32_nor_psram_config *confi
8877
static int memc_stm32_nor_psram_init(const struct device *dev)
8978
{
9079
const struct memc_stm32_nor_psram_config *config = dev->config;
91-
uint32_t memory_type;
80+
const struct memc_stm32_nor_psram_bank_config *bank_config;
9281
size_t bank_idx;
93-
int ret = 0;
82+
int ret;
9483

9584
for (bank_idx = 0U; bank_idx < config->banks_len; ++bank_idx) {
96-
memory_type = config->banks[bank_idx].init.MemoryType;
85+
bank_config = &config->banks[bank_idx];
9786

98-
switch (memory_type) {
87+
switch (bank_config->init.MemoryType) {
9988
case FMC_MEMORY_TYPE_NOR:
100-
ret = memc_stm32_nor_init(config, &config->banks[bank_idx]);
89+
ret = memc_stm32_nor_init(config, bank_config);
10190
break;
10291
case FMC_MEMORY_TYPE_PSRAM:
10392
__fallthrough;
10493
case FMC_MEMORY_TYPE_SRAM:
105-
ret = memc_stm32_psram_init(config, &config->banks[bank_idx]);
94+
ret = memc_stm32_psram_init(config, bank_config);
10695
break;
10796
default:
10897
ret = -ENOTSUP;
@@ -112,13 +101,13 @@ static int memc_stm32_nor_psram_init(const struct device *dev)
112101
if (ret < 0) {
113102
LOG_ERR("Unable to initialize memory type: "
114103
"0x%08X, NSBank: %d, err: %d",
115-
memory_type, config->banks[bank_idx].init.NSBank, ret);
116-
goto end;
104+
bank_config->init.MemoryType,
105+
bank_config->init.NSBank, ret);
106+
return ret;
117107
}
118108
}
119109

120-
end:
121-
return ret;
110+
return 0;
122111
}
123112

124113
/** SDRAM bank/s configuration initialization macro. */
@@ -165,9 +154,6 @@ static const struct memc_stm32_nor_psram_bank_config bank_config[] = {
165154

166155
/** SRAM configuration. */
167156
static const struct memc_stm32_nor_psram_config config = {
168-
.nor_psram = (FMC_NORSRAM_TypeDef *)(DT_REG_ADDR(DT_INST_PARENT(0)) + SRAM_OFFSET),
169-
.extended = (FMC_NORSRAM_EXTENDED_TypeDef *)(DT_REG_ADDR(DT_INST_PARENT(0))
170-
+ SRAM_EXT_OFFSET),
171157
.banks = bank_config,
172158
.banks_len = ARRAY_SIZE(bank_config),
173159
};

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