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drivers: pinctrl: microchip: add pinctrl driver for Port G1 IP
Add pinctrl driver for Microchip Port G1 Peripheral IPs Signed-off-by: Mohamed Azhar <[email protected]>
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‎drivers/pinctrl/CMakeLists.txt

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@@ -23,6 +23,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM0 pinctrl_sam0.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SAM_PIO4 pinctrl_sam_pio4.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_STM32 pinctrl_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_PORT pinctrl_nxp_port.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_PORT_G1 pinctrl_mchp_port_g1.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)

‎drivers/pinctrl/Kconfig

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@@ -46,6 +46,7 @@ source "drivers/pinctrl/Kconfig.it8xxx2"
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source "drivers/pinctrl/Kconfig.npcx"
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source "drivers/pinctrl/Kconfig.numicro"
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source "drivers/pinctrl/Kconfig.nrf"
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source "drivers/pinctrl/Kconfig.mchp"
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source "drivers/pinctrl/Kconfig.mspm0"
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source "drivers/pinctrl/Kconfig.rpi_pico"
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source "drivers/pinctrl/Kconfig.sam"

‎drivers/pinctrl/Kconfig.mchp

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# Copyright (c) 2025 Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_MCHP_PORT_G1
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bool "Microchip PORT G1 pin controller driver"
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default y
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depends on DT_HAS_MICROCHIP_PORT_G1_PINCTRL_ENABLED
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help
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This option enables PINCTRL driver for group (g1) of PORT peripherals.

‎drivers/pinctrl/pinctrl_mchp_port_g1.c

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file pinctrl_mchp_port_g1.c
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* @brief Pin control driver for Microchip devices.
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*
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* This file provides the implementation of pin control functions
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* for Microchip-based systems.
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <soc.h>
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/**
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* @brief Utility macro that expands to the PORT address if it exists.
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*
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* This macro checks if a node label exists in the device tree and, if it does,
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* it expands to the register address of that node label. If the node label does
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* not exist, it expands to nothing.
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*
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* @param nodelabel The node label to check in the device tree.
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*/
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/* clang-format off */
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#define MCHP_PORT_ADDR_OR_NONE(nodelabel) \
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IF_ENABLED(DT_NODE_EXISTS(DT_NODELABEL(nodelabel)), \
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(DT_REG_ADDR(DT_NODELABEL(nodelabel))))
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/* clang-format on */
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/**
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* @brief Array of port addresses for the MCHP SAMD5x_E5x series.
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*
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* This array contains the register addresses of the ports (PORTA, PORTB, PORTC, and PORTD)
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* for the MCHP SAMD5x_E5x series microcontrollers. The addresses are obtained using the
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* MCHP_PORT_ADDR_OR_NONE macro, which ensures that only existing ports are included.
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* This can be updated for other devices using conditional comiplation directives
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*/
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static const uint32_t mchp_port_addrs[] = {
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MCHP_PORT_ADDR_OR_NONE(porta),
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MCHP_PORT_ADDR_OR_NONE(portb),
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MCHP_PORT_ADDR_OR_NONE(portc),
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MCHP_PORT_ADDR_OR_NONE(portd),
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};
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/**
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* @brief Set pinmux registers using odd/even logic
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*
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* This function configures the pinmux registers for a given pin based on
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* the provided pin control information. It determines whether the pin number
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* is odd or even and sets the appropriate bits in the PORT_PMUX register.
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*
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* @param pin Pointer to the pin control information
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* @param reg Pointer to the base address of the port group registers
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*/
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static void pinctrl_pinmux(const pinctrl_soc_pin_t *pin)
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{
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port_group_registers_t *pRegister;
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uint8_t pin_num = MCHP_PINMUX_PIN_GET(pin->pinmux);
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uint8_t port_id = MCHP_PINMUX_PORT_GET(pin->pinmux);
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uint8_t pin_mux = MCHP_PINMUX_PERIPH_GET(pin->pinmux);
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bool is_odd = pin_num & 1;
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uint32_t idx = pin_num / 2U;
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pRegister = (port_group_registers_t *)mchp_port_addrs[port_id];
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if (pRegister != NULL) {
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/* Each pinmux register holds the config for two pins. The
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* even numbered pin goes in the bits 0..3 and the odd
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* numbered pin in bits 4..7.
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*/
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if (is_odd == true) {
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pRegister->PORT_PMUX[idx] |= PORT_PMUX_PMUXO(pin_mux);
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} else {
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pRegister->PORT_PMUX[idx] |= PORT_PMUX_PMUXE(pin_mux);
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}
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pRegister->PORT_PINCFG[pin_num] |= (uint8_t)PORT_PINCFG_PMUXEN_Msk;
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}
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}
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/**
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* @brief Set all pin configuration registers by checking the flags
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*
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* This function configures various pin settings such as pull-up, pull-down,
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* input enable, output enable, and drive strength based on the provided
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* pin control information.
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*
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* @param pin Pointer to the pin control information
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* @param reg Pointer to the base address of the port group registers
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*/
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static void pinctrl_set_flags(const pinctrl_soc_pin_t *pin)
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{
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port_group_registers_t *pRegister;
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uint8_t pin_num = MCHP_PINMUX_PIN_GET(pin->pinmux);
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uint8_t port_id = MCHP_PINMUX_PORT_GET(pin->pinmux);
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pRegister = (port_group_registers_t *)mchp_port_addrs[port_id];
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if (pRegister != NULL) {
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/* Check if pull-up or pull-down resistors need to be configured */
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if (((pin->pinflag & MCHP_PINCTRL_PULLUP) != 0) ||
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((pin->pinflag & MCHP_PINCTRL_PULLDOWN) != 0)) {
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if ((pin->pinflag & MCHP_PINCTRL_PULLUP) != 0) {
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/* If pull-up resistor enabled,
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* set the corresponding bit in PORT_OUT reg
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*/
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pRegister->PORT_OUT |= (1 << pin_num);
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}
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pRegister->PORT_PINCFG[pin_num] |= PORT_PINCFG_PULLEN(1);
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} else {
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pRegister->PORT_PINCFG[pin_num] &= ~PORT_PINCFG_PULLEN(1);
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}
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/* if input is enabled, set the corresponding bit in PORT_PINCFG register */
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if ((pin->pinflag & MCHP_PINCTRL_INPUTENABLE) != 0) {
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pRegister->PORT_PINCFG[pin_num] |= PORT_PINCFG_INEN(1);
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} else {
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pRegister->PORT_PINCFG[pin_num] &= ~PORT_PINCFG_INEN(1);
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}
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/* if output is enabled, set the corresponding bit in PORT_DIR register */
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if ((pin->pinflag & MCHP_PINCTRL_OUTPUTENABLE) != 0) {
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pRegister->PORT_DIR |= (1 << pin_num);
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} else {
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pRegister->PORT_DIR &= ~(1 << pin_num);
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}
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/* if drive strength is enabled, set the corresponding bit in PORT_PINCFG reg */
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if ((pin->pinflag & MCHP_PINCTRL_DRIVESTRENGTH) != 0) {
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pRegister->PORT_PINCFG[pin_num] |= PORT_PINCFG_DRVSTR(1);
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} else {
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pRegister->PORT_PINCFG[pin_num] &= ~PORT_PINCFG_DRVSTR(1);
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}
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}
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}
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/**
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* @brief Configure a specific pin based on the provided pin configuration.
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*
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* This helper function configures a pin by determining its port function and then
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* calling the appropriate functions to set the pinmux and other pin configurations.
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*
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* @param pin The pin configuration to be applied. This is of type pinctrl_soc_pin_t.
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*/
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static void pinctrl_configure_pin(pinctrl_soc_pin_t pin)
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{
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uint8_t port_func = MCHP_PINMUX_FUNC_GET(pin.pinmux);
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/* call pinmux function if alternate function is configured */
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if (port_func == MCHP_PINMUX_FUNC_periph) {
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pinctrl_pinmux(&pin);
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}
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/* set all other pin configurations */
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pinctrl_set_flags(&pin);
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}
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/**
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* @brief Configure multiple pins.
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*
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* This function configures a set of pins based on the provided pin
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* configuration array.
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*
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* @param pins Pointer to an array of pinctrl_soc_pin_t structures that
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* define the pin configurations.
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* @param pin_cnt Number of pins to configure.
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* @param reg Unused parameter.
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*
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* @return 0 on success.
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*/
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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pinctrl_configure_pin(*pins);
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pins++;
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}
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return 0;
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}

‎soc/microchip/sam/sam_d5x_e5x/CMakeLists.txt

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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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zephyr_include_directories(common)
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zephyr_include_directories(${SOC_SERIES})

‎soc/microchip/sam/sam_d5x_e5x/Kconfig.soc

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@@ -7,4 +7,15 @@ config SOC_FAMILY_MICROCHIP_SAM_D5X_E5X
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config SOC_FAMILY
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default "microchip_sam_d5x_e5x" if SOC_FAMILY_MICROCHIP_SAM_D5X_E5X
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# List of Peripheral IPs available in SOC_FAMILY_MICROCHIP_SAM_D5X_E5X family
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if SOC_FAMILY_MICROCHIP_SAM_D5X_E5X
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config PINCTRL_MCHP_PORT_U2210_2_2_0
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bool
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default y
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help
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Enable PORT pinctrl peripheral IP version 2.2.0 (U2210).
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endif # SOC_FAMILY_MICROCHIP_SAM_D5X_E5X
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rsource "*/Kconfig.soc"

‎soc/microchip/sam/sam_d5x_e5x/common/pinctrl_soc.h

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/*
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* Copyright (c) 2025 Microchip Technology Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SOC_MICROCHIP_SAM_D5X_E5X_COMMON_PINCTRL_SOC_H_
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#define SOC_MICROCHIP_SAM_D5X_E5X_COMMON_PINCTRL_SOC_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/types.h>
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#include "dt-bindings/sam/sam_d5x_e5x/common/mchp_pinctrl_pinmux_sam.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** @cond INTERNAL_HIDDEN */
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/**
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* @brief Structure representing the pin control settings for a SOC pin.
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*
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* This structure is used to define the pinmux and pin configuration settings
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* for a specific pin on the SOC. It includes information about the port, pin,
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* function, bias, drive, and other configuration options.
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*/
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typedef struct pinctrl_soc_pin {
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/** Pinmux settings (port, pin and function). */
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uint16_t pinmux;
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/** Pin configuration (bias, drive etc). */
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uint16_t pinflag;
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} pinctrl_soc_pin_t;
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/**
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* @brief Utility macro to initialize pinmux field.
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*
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* @param node_id Node identifier.
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*/
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#define Z_PINCTRL_MCHP_PINMUX_INIT(node_id, prop, idx) DT_PROP_BY_IDX(node_id, prop, idx)
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/**
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* @brief Utility macro to initialize each pin.
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*
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* @param node_id Node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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#define Z_PINCTRL_MCHP_PINFLAG_INIT(node_id, prop, idx) \
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((DT_PROP(node_id, bias_pull_up) << MCHP_PINCTRL_PULLUP_POS) | \
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(DT_PROP(node_id, bias_pull_down) << MCHP_PINCTRL_PULLDOWN_POS) | \
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(DT_PROP(node_id, input_enable) << MCHP_PINCTRL_INPUTENABLE_POS) | \
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(DT_PROP(node_id, output_enable) << MCHP_PINCTRL_OUTPUTENABLE_POS) | \
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(DT_ENUM_IDX(node_id, drive_strength) << MCHP_PINCTRL_DRIVESTRENGTH_POS)),
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/**
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* @brief Utility macro to initialize each pin.
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*
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* @param node_id Node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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{.pinmux = Z_PINCTRL_MCHP_PINMUX_INIT(node_id, prop, idx), \
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.pinflag = Z_PINCTRL_MCHP_PINFLAG_INIT(node_id, prop, idx)},
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/**
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* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
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*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
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Z_PINCTRL_STATE_PIN_INIT)}
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/** @endcond */
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/**
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* @brief Pin flags/attributes
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* @anchor MCHP_PINFLAGS
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*
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* @{
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*/
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#define MCHP_PINCTRL_FLAGS_DEFAULT (0U)
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#define MCHP_PINCTRL_FLAGS_POS (0U)
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#define MCHP_PINCTRL_FLAGS_MASK (0x3F << MCHP_PINCTRL_FLAGS_POS)
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#define MCHP_PINCTRL_FLAG_MASK (1U)
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#define MCHP_PINCTRL_PULLUP_POS (MCHP_PINCTRL_FLAGS_POS)
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#define MCHP_PINCTRL_PULLUP (1U << MCHP_PINCTRL_PULLUP_POS)
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#define MCHP_PINCTRL_PULLDOWN_POS (MCHP_PINCTRL_PULLUP_POS + 1U)
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#define MCHP_PINCTRL_PULLDOWN (1U << MCHP_PINCTRL_PULLDOWN_POS)
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#define MCHP_PINCTRL_OPENDRAIN_POS (MCHP_PINCTRL_PULLDOWN_POS + 1U)
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#define MCHP_PINCTRL_OPENDRAIN (1U << MCHP_PINCTRL_OPENDRAIN_POS)
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#define MCHP_PINCTRL_INPUTENABLE_POS (MCHP_PINCTRL_OPENDRAIN_POS + 1U)
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#define MCHP_PINCTRL_INPUTENABLE (1U << MCHP_PINCTRL_INPUTENABLE_POS)
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#define MCHP_PINCTRL_OUTPUTENABLE_POS (MCHP_PINCTRL_INPUTENABLE_POS + 1U)
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#define MCHP_PINCTRL_OUTPUTENABLE (1U << MCHP_PINCTRL_OUTPUTENABLE_POS)
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#define MCHP_PINCTRL_DRIVESTRENGTH_POS (MCHP_PINCTRL_OUTPUTENABLE_POS + 1U)
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#define MCHP_PINCTRL_DRIVESTRENGTH (1U << MCHP_PINCTRL_DRIVESTRENGTH_POS)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* SOC_MICROCHIP_SAM_D5X_E5X_COMMON_PINCTRL_SOC_H_ */

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