Devvicetree: Formating - fix doxygen comments

kylebonnici · kylebonnici · commit f6c062b7e2ed · 2025-07-22T19:59:19.000+02:00
Fix all doxygen comments and add some more improvment to comment
formating

Signed-off-by: Kyle Micallef Bonnici &lt;kylebonnici@hotmail.com&gt;
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi
@@ -144,7 +144,8 @@ zephyr_i2c: &i2c1 {
 		status = "okay";
 		mode-register = <0x220>;
 
-		/* * From Arduino github repository:
+		/**
+		 * From Arduino github repository:
 		 *  RefreshRate = 64 ms / 8192 cyc = 7.8125 us/cyc
 		 *  RefreshCycles = 7.8125 us * 90 MHz = 703
 		 *  According to the formula on p.1665 of the reference manual,
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts
@@ -68,7 +68,8 @@
 	status = "okay";
 };
 
-/* * The power supply for the Portenta H7 is based on a ST PSU reference design.
+/**
+ * The power supply for the Portenta H7 is based on a ST PSU reference design.
  *  The design specification from this reference design limits the maximum
  *  clock speed to 400 MHz.
  *        Refer: section 8.1 of the reference design guide.
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.overlay b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.overlay
@@ -1,4 +1,4 @@
-/* *
+/**
  * Copyright (c) 2024 Rahul Arasikere <arasikere.rahul@gmail.com>.
  *
  * SPDX-License-Identifier: Apache-2.0
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.overlay b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.overlay
@@ -1,4 +1,4 @@
-/* *
+/**
  * Copyright (c) 2024 Rahul Arasikere <arasikere.rahul@gmail.com>.
  *
  * SPDX-License-Identifier: Apache-2.0
diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.dts
@@ -43,7 +43,7 @@
 		};
 	};
 
-	/* *
+	/**
 	 * The BeagleConnect Freedom has an on-board antenna switch (SKY13317-373LF) used to select
 	 * the appropriate RF signal port based on the currently-used PHY.
 	 *
diff --git a/boards/beagle/beagleplay/beagleplay_cc1352p7.dts b/boards/beagle/beagleplay/beagleplay_cc1352p7.dts
@@ -40,7 +40,7 @@
 		};
 	};
 
-	/* *
+	/**
 	 * The BeaglePlay cc1352 has an on-board antenna switch (SKY13317-373LF) used to
 	 * select the appropriate RF signal port based on the currently-used PHY.
 	 *
diff --git a/boards/nxp/imx93_evk/dts/imx93_evk_mimx9352_exp_btn.overlay b/boards/nxp/imx93_evk/dts/imx93_evk_mimx9352_exp_btn.overlay
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/* *
+/**
  * Apply this overlay to test RFU_BTN1 and RFU_BTN2 on PCAL6524.
  *
  * The user buttons RFU_BTN1 and RFU_BTN2 is connected to i.MX 93 GPIO by default,
diff --git a/boards/phytec/reel_board/reel_board_nrf52840_2.overlay b/boards/phytec/reel_board/reel_board_nrf52840_2.overlay
@@ -53,31 +53,31 @@
 				gate-line-width = <0x0a>;
 				lut = [
 				       /*
-				       * Waveform Composition
-				       *
-				       * There are 7 Voltage Source (VS) Level groups
-				       * n = {0,1,2...6}, each group contains
-				       * 4 phases x = {A,B,C,D}.
-				       * 2 bits represent the voltage in a phase:
-				       * 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2
-				       *
-				       * For example 0x80 represents sequence VSL-VSS-VSS-VSS,
-				       */
+				        * Waveform Composition
+				        *
+				        * There are 7 Voltage Source (VS) Level groups
+				        * n = {0,1,2...6}, each group contains
+				        * 4 phases x = {A,B,C,D}.
+				        * 2 bits represent the voltage in a phase:
+				        * 00 – VSS, 01 – VSH1, 10 – VSL, 11 - VSH2
+				        *
+				        * For example 0x80 represents sequence VSL-VSS-VSS-VSS,
+				        */
 				       80 60 40 00 00 00 00	/* LUT0: BB: VS 0..6 */
 				       10 60 20 00 00 00 00	/* LUT1: BW: VS 0..6 */
 				       80 60 40 00 00 00 00	/* LUT2: WB: VS 0..6 */
 				       10 60 20 00 00 00 00	/* LUT3: WW: VS 0..6 */
 				       00 00 00 00 00 00 00	/* LUT4: VCOM: VS 0..6 */
 				       /*
-				       * TPnx determines the length of each phase,
-				       * and RPn repeat count of a sequence.
-				       * TPnA, TPnB, TPnC, TPnD, RPn
-				       *
-				       * For example TP0A=3, TP0B=3, and RP0=2:
-				       * VS sequence                    : VSL-VSS-VSS-VSS
-				       * number of Gate Pulses (length) :  3   3   0   0
-				       * repeat count                   :        2
-				       */
+				        * TPnx determines the length of each phase,
+				        * and RPn repeat count of a sequence.
+				        * TPnA, TPnB, TPnC, TPnD, RPn
+				        *
+				        * For example TP0A=3, TP0B=3, and RP0=2:
+				        * VS sequence                    : VSL-VSS-VSS-VSS
+				        * number of Gate Pulses (length) :  3   3   0   0
+				        * repeat count                   :        2
+				        */
 				       03 03 00 00 02	/* TP0A TP0B TP0C TP0D RP0 */
 				       09 09 00 00 02	/* TP1A TP1B TP1C TP1D RP1 */
 				       03 03 00 00 02	/* TP2A TP2B TP2C TP2D RP2 */
diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1.dts b/boards/renesas/ek_ra2l1/ek_ra2l1.dts
@@ -1,4 +1,4 @@
-/* *
+/**
  * Copyright (c) 2021-2024 MUNIC SA
  * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
diff --git a/boards/shields/openthread_rcp_arduino/openthread_rcp_arduino_serial.overlay b/boards/shields/openthread_rcp_arduino/openthread_rcp_arduino_serial.overlay
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/* *
+/**
  * Overlay to enable support for OpenThread's RCP over UART communication
  */
 
diff --git a/boards/shields/openthread_rcp_arduino/openthread_rcp_arduino_spi.overlay b/boards/shields/openthread_rcp_arduino/openthread_rcp_arduino_spi.overlay
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/* *
+/**
  * Overlay to enable support for OpenThread's RCP over SPI communication
  */
 
diff --git a/boards/st/nucleo_h503rb/st_morpho_connector.dtsi b/boards/st/nucleo_h503rb/st_morpho_connector.dtsi
@@ -17,8 +17,8 @@
 			   <ST_MORPHO_L_3 0 &gpioc 12 0>,
 			   <ST_MORPHO_L_4 0 &gpiod 2 0>,
 			   /* By default, PA13 and PA14 are used as SWD signals
-			   * (SB40=ON, SB41=ON)
-			   */
+			    * (SB40=ON, SB41=ON)
+			    */
 			   <ST_MORPHO_L_13 0 &gpioa 13 0>,
 			   <ST_MORPHO_L_15 0 &gpioa 14 0>,
 			   <ST_MORPHO_L_17 0 &gpioa 15 0>,
diff --git a/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts b/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts
@@ -116,7 +116,7 @@
 };
 
 &rtc {
-	/* *
+	/**
 	 * STM32_SRC_LSE reflects the "slow-clock" selected on RCC node.
 	 * NO_SEL reflects STM32WB0's lack of RTC clock mux to configure.
 	 */
diff --git a/boards/st/nucleo_wb07cc/nucleo_wb07cc.dts b/boards/st/nucleo_wb07cc/nucleo_wb07cc.dts
@@ -115,7 +115,7 @@
 };
 
 &rtc {
-	/* *
+	/**
 	 * STM32_SRC_LSE reflects the "slow-clock" selected on RCC node.
 	 * NO_SEL reflects STM32WB0's lack of RTC clock mux to configure.
 	 */
diff --git a/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts b/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts
@@ -116,7 +116,7 @@
 };
 
 &rtc {
-	/* *
+	/**
 	 * STM32_SRC_LSE reflects the "slow-clock" selected on RCC node.
 	 * NO_SEL reflects STM32WB0's lack of RTC clock mux to configure.
 	 */
diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi
@@ -365,7 +365,7 @@ zephyr_udc0: &usbotg_hs1 {
 	};
 };
 
-/* *
+/**
  * Per the RGMII specification, the Tx clock signal must be skewed
  * from the Tx data signals by 1~2 ns. On this board, the SoC must
  * be configured to add the required delay via pinctrl.
@@ -403,7 +403,7 @@ zephyr_udc0: &usbotg_hs1 {
 	eth_phy: ethernet-phy@1 {
 		compatible = "realtek,rtl8211f";
 		reg = <0x1>;
-		/* *
+		/**
 		 * PD3 can be used as alternate function ETH1_PHY_INTN,
 		 * which allows the Ethernet MAC to sense interrupts from
 		 * the PHY in order to signal them to the CPU via its own
diff --git a/boards/ti/common/launchxl_sky13317.dtsi b/boards/ti/common/launchxl_sky13317.dtsi
@@ -5,7 +5,7 @@
  */
 
 / {
-	/* *
+	/**
 	 * The CC1352P LAUNCHXL has an on-board antenna switch (SKY13317-373LF) used to select the
 	 * appropriate RF signal port based on the currently-used PHY.
 	 *

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-/* *`
	`1`	`+/**`
`2`	`2`	`* Copyright (c) 2024 Rahul Arasikere <[email protected]>.`
`3`	`3`	`*`
`4`	`4`	`* SPDX-License-Identifier: Apache-2.0`
Original file line number	Diff line number	Diff line change
`@@ -43,7 +43,7 @@`
`43`	`43`	`};`
`44`	`44`	`};`
`45`	`45`
`46`		`- /* *`
	`46`	`+ /**`
`47`	`47`	`* The BeagleConnect Freedom has an on-board antenna switch (SKY13317-373LF) used to select`
`48`	`48`	`* the appropriate RF signal port based on the currently-used PHY.`
`49`	`49`	`*`
Original file line number	Diff line number	Diff line change
`@@ -40,7 +40,7 @@`
`40`	`40`	`};`
`41`	`41`	`};`
`42`	`42`
`43`		`- /* *`
	`43`	`+ /**`
`44`	`44`	`* The BeaglePlay cc1352 has an on-board antenna switch (SKY13317-373LF) used to`
`45`	`45`	`* select the appropriate RF signal port based on the currently-used PHY.`
`46`	`46`	`*`
Original file line number	Diff line number	Diff line change
`@@ -4,7 +4,7 @@`
`4`	`4`	`* SPDX-License-Identifier: Apache-2.0`
`5`	`5`	`*/`
`6`	`6`
`7`		`-/* *`
	`7`	`+/**`
`8`	`8`	`* Apply this overlay to test RFU_BTN1 and RFU_BTN2 on PCAL6524.`
`9`	`9`	`*`
`10`	`10`	`* The user buttons RFU_BTN1 and RFU_BTN2 is connected to i.MX 93 GPIO by default,`