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Add DMA driver support for Texas Instruments MSPM0 Family Series

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struct dma_mspm0_channel_data {
uint8_t direction;
bool busy;
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move these 2 at the end for better alignment

@parthitce parthitce linked an issue Jun 26, 2025 that may be closed by this pull request
@karthi012 karthi012 force-pushed the upstream/ti/mspm0-dma branch from 1109426 to 1778ccb Compare July 24, 2025 14:28
@karthi012 karthi012 marked this pull request as ready for review July 24, 2025 14:32
@zephyrbot zephyrbot added area: DMA Direct Memory Access platform: TI SimpleLink Texas Instruments SimpleLink MCU platform: Texas Instruments MSPM0 labels Jul 24, 2025
@karthi012 karthi012 requested a review from tbursztyka July 24, 2025 14:34
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@teburd @vaishnavachath @tbursztyka Ping for review

break;
default:
return -EINVAL;
}
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@teburd teburd Jul 24, 2025

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Some funky formatting here needs to be fixed.

I recommend trying to use clang-format on the file to make it easier now and in the future to make changes. Disabling formatting for certain macros and such is just fine. If it doesn't work it doesn't work, but worth a go.

return -EINVAL;
}

dma_cfg.destWidth = temp;
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Some formatting issues here

Add DMA driver binding for Texas Instruments MSPM0 Family Series

Signed-off-by: Karthikeyan Krishnasamy <[email protected]>
Add DMA driver support for Texas Instruments MSPM0 Family Series.

Signed-off-by: Karthikeyan Krishnasamy <[email protected]>
Add DMA controller support for Texas Instruments MSPM0 Family of SoCs.

Signed-off-by: Karthikeyan Krishnasamy <[email protected]>
@karthi012 karthi012 force-pushed the upstream/ti/mspm0-dma branch from c412d28 to 6bdf294 Compare September 20, 2025 13:49
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@karthi012 karthi012 requested a review from teburd September 20, 2025 14:28
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should be added to a test case to ensure it builds and remains building

dma_cfg.triggerType = DL_DMA_TRIGGER_TYPE_EXTERNAL;
dma_cfg.trigger = config->dma_slot;

DL_DMA_clearInterruptStatus(DMA, channel + DMA_TI_MSPM0_BASE_CHANNEL_NUM);
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It's unclear here if there are any shared registers, but if any register is shared the register update needs to be done inside a spin lock (critical section)

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DMA: Core driver
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