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devicetree: format files in dts #92803

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fdd7338
devicetree: format files in dts/arc/synopsys
kylebonnici Jul 8, 2025
e8575ce
devicetree: format files in dts/arm/acsip
kylebonnici Jul 8, 2025
09ab788
devicetree: format files in dts/arm/adi
kylebonnici Jul 8, 2025
b38da55
devicetree: format files in dts/arm/ambiq
kylebonnici Jul 8, 2025
168e6ac
devicetree: format files in dts/arm/atmel
kylebonnici Jul 8, 2025
42fce27
devicetree: format files in dts/arm/ene
kylebonnici Jul 8, 2025
46892fc
devicetree: format files in dts/arm/gd
kylebonnici Jul 8, 2025
ab50c10
devicetree: format files in dts/arm/infineon
kylebonnici Jul 8, 2025
68e00b1
devicetree: format files in dts/arm/intel_socfpga_std
kylebonnici Jul 8, 2025
1356090
devicetree: format files in dts/arm/microchip
kylebonnici Jul 8, 2025
f677100
devicetree: format files in dts/arm/nordic
kylebonnici Jul 8, 2025
22b8c00
devicetree: format files in dts/arm/nuvoton
kylebonnici Jul 8, 2025
843c69a
devicetree: format files in dts/arm/nxp
kylebonnici Jul 8, 2025
7eba091
devicetree: format files in dts/arm/olimex
kylebonnici Jul 8, 2025
dc210bc
devicetree: format files in dts/arm/rakwireless
kylebonnici Jul 8, 2025
fbe7fd0
devicetree: format files in dts/arm/raspberrypi
kylebonnici Jul 8, 2025
30046ca
devicetree: format files in dts/arm/realtek
kylebonnici Jul 8, 2025
95038b6
devicetree: format files in dts/arm/renesas
kylebonnici Jul 8, 2025
43a1ef9
devicetree: format files in dts/arm/silabs
kylebonnici Jul 8, 2025
a3f770d
devicetree: format files in dts/arm/st
kylebonnici Jul 8, 2025
84642b8
devicetree: format files in dts/arm/ti
kylebonnici Jul 8, 2025
468d13c
devicetree: format files in dts/arm/we
kylebonnici Jul 8, 2025
77f6335
devicetree: format files in dts/arm/xilinx
kylebonnici Jul 8, 2025
1b263b4
devicetree: format files in dts/arm64/broadcom
kylebonnici Jul 8, 2025
3a52e8b
devicetree: format files in dts/arm64/intel
kylebonnici Jul 8, 2025
a33b882
devicetree: format files in dts/arm64/nxp
kylebonnici Jul 8, 2025
dc05503
devicetree: format files in dts/arm64/qemu
kylebonnici Jul 8, 2025
42308ce
devicetree: format files in dts/arm64/renesas
kylebonnici Jul 8, 2025
8f3946a
devicetree: format files in dts/arm64/rockchip
kylebonnici Jul 8, 2025
0f4fa49
devicetree: format files in dts/arm64/ti
kylebonnici Jul 8, 2025
caef4d6
devicetree: format files in dts/riscv/bflb
kylebonnici Jul 8, 2025
24de07f
devicetree: format files in dts/riscv/efinix
kylebonnici Jul 8, 2025
0c442d3
devicetree: format files in dts/riscv/espressif
kylebonnici Jul 8, 2025
d048f9e
devicetree: format files in dts/riscv/gd
kylebonnici Jul 8, 2025
015c492
devicetree: format files in dts/riscv/ite
kylebonnici Jul 8, 2025
90ee6b3
devicetree: format files in dts/riscv/lowrisc
kylebonnici Jul 8, 2025
b0a4d1e
devicetree: format files in dts/riscv/microchip
kylebonnici Jul 8, 2025
ab48747
devicetree: format files in dts/riscv/nordic
kylebonnici Jul 8, 2025
d525792
devicetree: format files in dts/riscv/openhwgroup
kylebonnici Jul 8, 2025
716b51e
devicetree: format files in dts/riscv/openisa
kylebonnici Jul 8, 2025
cacea0a
devicetree: format files in dts/riscv/qemu
kylebonnici Jul 8, 2025
ad1dbb6
devicetree: format files in dts/riscv/sensry
kylebonnici Jul 8, 2025
ce77764
devicetree: format files in dts/riscv/sifive
kylebonnici Jul 8, 2025
a36383e
devicetree: format files in dts/riscv/starfive
kylebonnici Jul 8, 2025
55149aa
devicetree: format files in dts/riscv/telink
kylebonnici Jul 8, 2025
ebb3729
devicetree: format files in dts/riscv/wch
kylebonnici Jul 8, 2025
0784a57
devicetree: format files in dts/rx/renesas
kylebonnici Jul 8, 2025
d24593f
devicetree: format files in dts/vendor/broadcom
kylebonnici Jul 8, 2025
e5efae8
devicetree: format files in dts/vendor/nordic
kylebonnici Jul 8, 2025
71ce034
devicetree: format files in dts/vendor/raspberrypi
kylebonnici Jul 8, 2025
505bced
devicetree: format files in dts/x86/intel
kylebonnici Jul 8, 2025
dade22d
devicetree: format files in dts/xtensa/espressif
kylebonnici Jul 8, 2025
9134520
devicetree: format files in dts/xtensa/intel
kylebonnici Jul 8, 2025
88542c5
devicetree: format files in dts/xtensa/nxp
kylebonnici Jul 8, 2025
42bdb1a
devicetree: format SoC-level files in dts/arm
kylebonnici Jul 8, 2025
2c10799
devicetree: format SoC-level files in dts/riscv
kylebonnici Jul 8, 2025
76c7403
devicetree: format SoC-level files in dts/xtensa
kylebonnici Jul 8, 2025
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4 changes: 1 addition & 3 deletions dts/arc/synopsys/arc_hs4xd.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,6 @@
compatible = "snps,archs4xd";
reg = <3>;
};

};

intc: arcv2-intc {
Expand All @@ -46,7 +45,6 @@
#interrupt-cells = <2>;
};


idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
Expand Down Expand Up @@ -101,7 +99,7 @@
status = "disabled";
};

uart1: uart@f0027000{
uart1: uart@f0027000 {
compatible = "ns16550";
clock-frequency = <33333333>;
reg = <0xf0027000 0x100>;
Expand Down
5 changes: 1 addition & 4 deletions dts/arc/synopsys/arc_hsdk.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,6 @@
compatible = "snps,archs38";
reg = <3>;
};

};

intc: arcv2-intc {
Expand All @@ -46,7 +45,6 @@
#interrupt-cells = <2>;
};


idu_intc: idu-interrupt-controller {
compatible = "snps,archs-idu-intc";
interrupt-controller;
Expand Down Expand Up @@ -92,7 +90,7 @@
reg-shift = <2>;
};

uart1: uart@f0026000{
uart1: uart@f0026000 {
compatible = "ns16550";
clock-frequency = <33333333>;
reg = <0xf0026000 0x1000>;
Expand Down Expand Up @@ -210,6 +208,5 @@
max-xfer-size = <16>;
status = "disabled";
};

};
};
4 changes: 0 additions & 4 deletions dts/arc/synopsys/arc_iot.dtsi
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Expand Up @@ -48,7 +48,6 @@
reg = <0x80000000 0x20000>;
};


sram: memory@30000000 {
compatible = "mmio-sram";
reg = <0x30000000 0x20000>;
Expand All @@ -71,7 +70,6 @@
compatible = "simple-bus";
ranges;


uart0: uart@80014000 {
compatible = "ns16550";
clock-frequency = <16000000>;
Expand Down Expand Up @@ -191,7 +189,6 @@
status = "disabled";
};


i2c0: i2c@80012000 {
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
Expand Down Expand Up @@ -266,6 +263,5 @@
interrupt-parent = <&intc>;
status = "disabled";
};

};
};
1 change: 0 additions & 1 deletion dts/arc/synopsys/emsdp.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,6 @@
compatible = "simple-bus";
ranges;


uart0: uart@f0004000 {
compatible = "ns16550";
clock-frequency = <DT_APB_CLK_HZ>;
Expand Down
4 changes: 0 additions & 4 deletions dts/arc/synopsys/emsk.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -57,7 +57,6 @@
reg = <0x10000000 0x8000000>;
};


i2c0: i2c@f0004000 {
compatible = "snps,designware-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
Expand Down Expand Up @@ -151,7 +150,6 @@
max-xfer-size = <16>;
#address-cells = <1>;
#size-cells = <0>;

};

spi1: spi@f0007000 {
Expand All @@ -163,8 +161,6 @@
max-xfer-size = <16>;
#address-cells = <1>;
#size-cells = <0>;

};

};
};
25 changes: 12 additions & 13 deletions dts/arm/acsip/s76s.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/


#include <st/l0/stm32l073Xz.dtsi>
#include <st/l0/stm32l073r(b-z)tx-pinctrl.dtsi>

Expand All @@ -21,18 +20,18 @@
/* SX1276 nRESET */
reset-gpios = <&gpiob 10 GPIO_ACTIVE_LOW>;
dio-gpios =
/* SX1276 D0 */
<&gpiob 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
/* SX1276 D1 */
<&gpioc 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
/* SX1276 D2 */
<&gpiob 9 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
/* SX1276 D3 */
<&gpiob 4 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
/* SX1276 D4 */
<&gpiob 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
/* SX1276 D5 */
<&gpioa 15 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
/* SX1276 D0 */
<&gpiob 11 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
/* SX1276 D1 */
<&gpioc 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
/* SX1276 D2 */
<&gpiob 9 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
/* SX1276 D3 */
<&gpiob 4 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
/* SX1276 D4 */
<&gpiob 3 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
/* SX1276 D5 */
<&gpioa 15 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
spi-max-frequency = <1000000>;
power-amplifier-output = "pa-boost";
};
Expand Down
6 changes: 3 additions & 3 deletions dts/arm/adi/max32/max32650.dtsi
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Expand Up @@ -175,15 +175,15 @@
status = "disabled";
};

wdt0: watchdog@40003000 {
wdt0: watchdog@40003000 {
compatible = "adi,max32-watchdog";
reg = <0x40003000 0x400>;
interrupts = <1 0>;
clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
status = "disabled";
};

wdt1: watchdog@40003400 {
wdt1: watchdog@40003400 {
compatible = "adi,max32-watchdog";
reg = <0x40003400 0x400>;
interrupts = <57 0>;
Expand All @@ -196,7 +196,7 @@
reg = <0x40028000 0x1000>;
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>,
<72 0>, <73 0>, <74 0>, <75 0>, <76 0>, <77 0>, <78 0>, <79 0>;
<72 0>, <73 0>, <74 0>, <75 0>, <76 0>, <77 0>, <78 0>, <79 0>;
dma-channels = <16>;
status = "disabled";
#dma-cells = <2>;
Expand Down
1 change: 0 additions & 1 deletion dts/arm/adi/max32/max32655-pinctrl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -401,7 +401,6 @@
/omit-if-no-ref/ wakeup_p3_1: wakeup_p3_1 {
pinmux = <MAX32_PINMUX(3, 1, AF2)>;
};

};
};
};
Expand Down
2 changes: 1 addition & 1 deletion dts/arm/adi/max32/max32655.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -85,7 +85,7 @@
#dma-cells = <2>;
};

wdt1: watchdog@40080800 {
wdt1: watchdog@40080800 {
compatible = "adi,max32-watchdog";
reg = <0x40080800 0x400>;
interrupts = <57 0>;
Expand Down
8 changes: 4 additions & 4 deletions dts/arm/adi/max32/max32657_common.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -43,21 +43,21 @@
clk_inro: clk_inro {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = < DT_FREQ_K(8) >;
clock-frequency = <DT_FREQ_K(8)>;
status = "disabled";
};

clk_ibro: clk_ibro {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = < 7372800 >;
clock-frequency = <7372800>;
status = "disabled";
};

clk_ertco: clk_ertco {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = < 32768 >;
clock-frequency = <32768>;
status = "disabled";
};

Expand Down Expand Up @@ -146,7 +146,7 @@
status = "disabled";
};

wdt0: watchdog@3000 {
wdt0: watchdog@3000 {
compatible = "adi,max32-watchdog";
reg = <0x3000 0x400>;
interrupts = <1 0>;
Expand Down
2 changes: 1 addition & 1 deletion dts/arm/adi/max32/max32660.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@
/delete-node/ &flash0;

&flc0 {
flash0: flash@0{
flash0: flash@0 {
compatible = "soc-nv-flash";
reg = <0x00000000 DT_SIZE_K(256)>;
write-block-size = <16>;
Expand Down
2 changes: 0 additions & 2 deletions dts/arm/adi/max32/max32662-pinctrl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -266,8 +266,6 @@
pinmux = <MAX32_PINMUX(0, 13, AF4)>;
};



/omit-if-no-ref/ pt0a_p0_14: pt0a_p0_14 {
pinmux = <MAX32_PINMUX(0, 14, AF1)>;
};
Expand Down
1 change: 0 additions & 1 deletion dts/arm/adi/max32/max32670-pinctrl.dtsi
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Expand Up @@ -361,7 +361,6 @@
/omit-if-no-ref/ tmr3c_ia_p0_30: tmr3c_ia_p0_30 {
pinmux = <MAX32_PINMUX(0, 30, AF3)>;
};

};
};
};
Expand Down
2 changes: 1 addition & 1 deletion dts/arm/adi/max32/max32670.dtsi
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Expand Up @@ -83,7 +83,7 @@
#dma-cells = <2>;
};

wdt1: watchdog@40003400 {
wdt1: watchdog@40003400 {
compatible = "adi,max32-watchdog";
reg = <0x40003400 0x400>;
interrupts = <57 0>;
Expand Down
4 changes: 2 additions & 2 deletions dts/arm/adi/max32/max32672.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -103,13 +103,13 @@
reg = <0x40028000 0x1000>;
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
interrupts = <28 0>, <29 0>, <30 0>, <31 0>, <68 0>, <69 0>, <70 0>, <71 0>,
<72 0>, <73 0>, <74 0>, <75 0>;
<72 0>, <73 0>, <74 0>, <75 0>;
dma-channels = <12>;
status = "disabled";
#dma-cells = <2>;
};

wdt1: watchdog@40003400 {
wdt1: watchdog@40003400 {
compatible = "adi,max32-watchdog";
reg = <0x40003400 0x400>;
interrupts = <57 0>;
Expand Down
2 changes: 1 addition & 1 deletion dts/arm/adi/max32/max32680.dtsi
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Expand Up @@ -67,7 +67,7 @@
#dma-cells = <2>;
};

wdt1: watchdog@40080800 {
wdt1: watchdog@40080800 {
compatible = "adi,max32-watchdog";
reg = <0x40080800 0x400>;
interrupts = <57 0>;
Expand Down
1 change: 0 additions & 1 deletion dts/arm/adi/max32/max32690-pinctrl.dtsi
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Expand Up @@ -765,7 +765,6 @@
/omit-if-no-ref/ lptmr1b_ioa_p3_7: lptmr1b_ioa_p3_7 {
pinmux = <MAX32_PINMUX(3, 7, AF2)>;
};

};
};
};
Expand Down
2 changes: 1 addition & 1 deletion dts/arm/adi/max32/max32690.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -197,7 +197,7 @@
#dma-cells = <2>;
};

wdt1: watchdog@40080800 {
wdt1: watchdog@40080800 {
compatible = "adi,max32-watchdog";
reg = <0x40080800 0x400>;
interrupts = <57 0>;
Expand Down
2 changes: 1 addition & 1 deletion dts/arm/adi/max32/max32xxx.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -218,7 +218,7 @@
status = "disabled";
};

wdt0: watchdog@40003000 {
wdt0: watchdog@40003000 {
compatible = "adi,max32-watchdog";
reg = <0x40003000 0x400>;
interrupts = <1 0>;
Expand Down
4 changes: 2 additions & 2 deletions dts/arm/adi/max32/max78000.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -32,7 +32,7 @@
};

gpio3: gpio@40080600 {
reg = <0x40080600 0x200>; // Address and size are dummy.
reg = <0x40080600 0x200>; // Address and size are dummy.
compatible = "adi,max32-gpio";
gpio-controller;
#gpio-cells = <2>;
Expand Down Expand Up @@ -106,7 +106,7 @@
status = "disabled";
};

wdt1: watchdog@40080800 {
wdt1: watchdog@40080800 {
compatible = "adi,max32-watchdog";
reg = <0x40080800 0x400>;
interrupts = <57 0>;
Expand Down
1 change: 0 additions & 1 deletion dts/arm/adi/max32/max78002-pinctrl.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -449,7 +449,6 @@
/omit-if-no-ref/ wakeup_p3_1: wakeup_p3_1 {
pinmux = <MAX32_PINMUX(3, 1, AF2)>;
};

};
};
};
4 changes: 2 additions & 2 deletions dts/arm/adi/max32/max78002.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -56,7 +56,7 @@
};

gpio3: gpio@40080600 {
reg = <0x40080600 0x200>; // Address and size are dummy.
reg = <0x40080600 0x200>; // Address and size are dummy.
compatible = "adi,max32-gpio";
gpio-controller;
#gpio-cells = <2>;
Expand Down Expand Up @@ -153,7 +153,7 @@
#dma-cells = <2>;
};

wdt1: watchdog@40080800 {
wdt1: watchdog@40080800 {
compatible = "adi,max32-watchdog";
reg = <0x40080800 0x400>;
interrupts = <57 0>;
Expand Down
6 changes: 3 additions & 3 deletions dts/arm/ambiq/ambiq_apollo3_blue.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -370,9 +370,9 @@
gpio-map-mask = <0xffffffe0 0xffffffc0>;
gpio-map-pass-thru = <0x1f 0x3f>;
gpio-map = <
0x00 0x0 &gpio0_31 0x0 0x0
0x20 0x0 &gpio32_63 0x0 0x0
>;
0x00 0x0 &gpio0_31 0x0 0x0
0x20 0x0 &gpio32_63 0x0 0x0
>;
reg = <0x40010000>;
#gpio-cells = <2>;
#address-cells = <1>;
Expand Down
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