enable irqsteer for m33 of imx943

boards/nxp/imx943_evk/imx943_evk_mimx94398_m33.dts

@@ -137,3 +137,7 @@
 	zephyr,random-mac-address;
 	status = "disabled";
 };
+
+&edma4 {
+	status = "okay";
+};

drivers/dma/dma_mcux_edma.c

@@ -871,6 +871,8 @@ static int dma_mcux_edma_get_status(const struct device *dev, uint32_t channel,
 	LOG_DBG("DMA CHx_ES 0x%x",  DEV_BASE(dev)->TCD[hw_channel].CH_ES);
 	LOG_DBG("DMA CHx_INT 0x%x", DEV_BASE(dev)->TCD[hw_channel].CH_INT);
 	LOG_DBG("DMA TCD_CSR 0x%x", DEV_BASE(dev)->TCD[hw_channel].CSR);
+	LOG_DBG("DMA TCD_SADDR 0x%x", DEV_BASE(dev)->TCD[hw_channel].SADDR);
+	LOG_DBG("DMA TCD_DADDR 0x%x", DEV_BASE(dev)->TCD[hw_channel].DADDR);
 #else
 	LOG_DBG("DMA CR 0x%x", DEV_BASE(dev)->CR);
 	LOG_DBG("DMA INT 0x%x", DEV_BASE(dev)->INT);
@@ -946,11 +948,11 @@ static int dma_mcux_edma_init(const struct device *dev)
 
 #define IRQ_CONFIG(n, idx, fn)							\
 	{									\
-		IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, idx, irq),			\
+		IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, idx),			\
 			    DT_INST_IRQ_BY_IDX(n, idx, priority),		\
 			    fn,							\
 			    DEVICE_DT_INST_GET(n), 0);				\
-			    irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq));	\
+			    irq_enable(DT_INST_IRQN_BY_IDX(n, idx));	\
 	}
 
 #define EDMA_CHANNELS_MASK(n) static uint32_t edma_channel_mask_##n[] =  \

drivers/interrupt_controller/Kconfig.nxp_irqsteer

@@ -1,6 +1,9 @@
 # Copyright 2023 NXP
 # SPDX-License-Identifier: Apache-2.0
 
+IRQSTEER_COMPAT := $(DT_COMPAT_NXP_IRQSTEER_INTC)
+REV_PROP := nxp,version
+
 config NXP_IRQSTEER
 	bool "IRQ_STEER interrupt controller for NXP chips"
 	default y
@@ -11,3 +14,10 @@ config NXP_IRQSTEER
 		multiple interrupts from peripheral to one or
 		more CPU interrupt lines. This is used for CPUs
 		such as XTENSA DSPs.
+
+config INTC_MCUX_IRQSTEER_V1
+	bool "MCUX IRQSTEER v1 driver"
+	default y
+	depends on $(dt_compat_any_has_prop,$(IRQSTEER_COMPAT),$(REV_PROP),1) && NXP_IRQSTEER
+	help
+	  IRQSTEER version 1 driver(drivers/irqsteer_1 in mcuxsdk) for MCUX series SoCs.

drivers/interrupt_controller/intc_nxp_irqsteer.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023,2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -261,9 +261,10 @@ LOG_MODULE_REGISTER(nxp_irqstr);
 	DT_FOREACH_CHILD_STATUS_OKAY_SEP(parent_id, _IRQSTEER_REGISTER_DISPATCHER, (;))
 
 /* utility macros */
-#define UINT_TO_IRQSTEER(x) ((IRQSTEER_Type *)(x))
 #define DISPATCHER_REGMAP(disp) \
 	(((const struct irqsteer_config *)disp->dev->config)->regmap_phys)
+#define DISPATCHER_MASTER_INDEX(disp) \
+	((int32_t)((const struct irqsteer_dispatcher *)disp->master_index))
 
 #if defined(CONFIG_XTENSA)
 #define irqstr_l1_irq_enable_raw(irq)     xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq))
@@ -277,6 +278,12 @@ LOG_MODULE_REGISTER(nxp_irqstr);
 #error ARCH not supported
 #endif
 
+#if defined(CONFIG_INTC_MCUX_IRQSTEER_V1)
+#define IRQSTEER_ADDR_OR_INST_INDEX(x) ((int32_t)(x))
+#else
+#define UINT_TO_IRQSTEER(x) ((IRQSTEER_Type *)(x))
+#define IRQSTEER_ADDR_OR_INST_INDEX(x) (UINT_TO_IRQSTEER(x))
+#endif
 struct irqsteer_config {
 	uint32_t regmap_phys;
 	uint32_t regmap_size;
@@ -310,7 +317,7 @@ static int to_zephyr_irq(uint32_t regmap, uint32_t irq,
 	idx = irq - FSL_FEATURE_IRQSTEER_IRQ_START_INDEX;
 
 	for (i = dispatcher->master_index - 1; i >= 0; i--) {
-		idx -= IRQSTEER_GetMasterIrqCount(UINT_TO_IRQSTEER(regmap), i);
+		idx -= IRQSTEER_GetMasterIrqCount(IRQSTEER_ADDR_OR_INST_INDEX(regmap), i);
 	}
 
 	return irq_to_level_2(idx) | dispatcher->irq;
@@ -322,7 +329,7 @@ static int to_system_irq(uint32_t regmap, int irq, int master_index)
 	int i;
 
 	for (i = master_index - 1; i >= 0; i--) {
-		irq += IRQSTEER_GetMasterIrqCount(UINT_TO_IRQSTEER(regmap), i);
+		irq += IRQSTEER_GetMasterIrqCount(IRQSTEER_ADDR_OR_INST_INDEX(regmap), i);
 	}
 
 	return irq + FSL_FEATURE_IRQSTEER_IRQ_START_INDEX;
@@ -336,7 +343,7 @@ static int from_zephyr_irq(uint32_t regmap, uint32_t irq, uint32_t master_index)
 	idx = irq;
 
 	for (i = 0; i < master_index; i++) {
-		idx += IRQSTEER_GetMasterIrqCount(UINT_TO_IRQSTEER(regmap), i);
+		idx += IRQSTEER_GetMasterIrqCount(IRQSTEER_ADDR_OR_INST_INDEX(regmap), i);
 	}
 
 	return idx + FSL_FEATURE_IRQSTEER_IRQ_START_INDEX;
@@ -357,13 +364,15 @@ static void irqstr_l1_irq_enable_disable(uint32_t irq,
 		irqstr_l1_irq_enable_raw(irq);
 
 		if (disp) {
-			IRQSTEER_EnableMasterInterrupt(UINT_TO_IRQSTEER(DISPATCHER_REGMAP(disp)),
-						       irq);
+			IRQSTEER_EnableMasterInterrupt(
+					IRQSTEER_ADDR_OR_INST_INDEX(DISPATCHER_REGMAP(disp)),
+					DISPATCHER_MASTER_INDEX(disp));
 		}
 	} else {
 		if (disp) {
-			IRQSTEER_DisableMasterInterrupt(UINT_TO_IRQSTEER(DISPATCHER_REGMAP(disp)),
-							irq);
+			IRQSTEER_DisableMasterInterrupt(
+					IRQSTEER_ADDR_OR_INST_INDEX(DISPATCHER_REGMAP(disp)),
+					DISPATCHER_MASTER_INDEX(disp));
 		}
 
 		irqstr_l1_irq_disable_raw(irq);
@@ -439,9 +448,9 @@ static void _irqstr_enable_disable_irq(struct irqsteer_dispatcher *disp,
 	uint32_t regmap = DISPATCHER_REGMAP(disp);
 
 	if (enable) {
-		IRQSTEER_EnableInterrupt(UINT_TO_IRQSTEER(regmap), system_irq);
+		IRQSTEER_EnableInterrupt(IRQSTEER_ADDR_OR_INST_INDEX(regmap), system_irq);
 	} else {
-		IRQSTEER_DisableInterrupt(UINT_TO_IRQSTEER(regmap), system_irq);
+		IRQSTEER_DisableInterrupt(IRQSTEER_ADDR_OR_INST_INDEX(regmap), system_irq);
 	}
 }
 
@@ -603,7 +612,7 @@ static void irqsteer_isr_dispatcher(const void *data)
 	cfg = dispatcher->dev->config;
 
 	/* fetch master interrupts status */
-	status = IRQSTEER_GetMasterInterruptsStatus(UINT_TO_IRQSTEER(cfg->regmap_phys),
+	status = IRQSTEER_GetMasterInterruptsStatus(IRQSTEER_ADDR_OR_INST_INDEX(cfg->regmap_phys),
 						    dispatcher->master_index);
 
 	for (i = 0; status; i++) {
@@ -637,6 +646,7 @@ __maybe_unused static int irqstr_pm_action(const struct device *dev,
 static int irqsteer_init(const struct device *dev)
 {
 	IRQSTEER_REGISTER_DISPATCHERS(DT_NODELABEL(irqsteer));
+	IRQSTEER_Init(IRQSTEER_ADDR_OR_INST_INDEX(DT_REG_ADDR(DT_NODELABEL(irqsteer))));
 
 	return pm_device_runtime_enable(dev);
 }

dts/arm/nxp/nxp_imx943_m33.dtsi

@@ -137,6 +137,34 @@
 			status = "disabled";
 		};
 
+		edma4: dma@42df0000 {
+			compatible = "nxp,mcux-edma";
+			reg = <0x42df0000 0x210000>;
+			interrupt-parent = <&irqsteer_master2>;
+			interrupts = <0 0>, <1 0>,
+				<2 0>, <3 0>,
+				<4 0>, <5 0>,
+				<6 0>, <7 0>,
+				<8 0>, <9 0>,
+				<10 0>, <11 0>,
+				<12 0>, <13 0>,
+				<14 0>, <15 0>,
+				<16 0>, <17 0>,
+				<18 0>, <19 0>,
+				<20 0>, <21 0>,
+				<22 0>, <23 0>,
+				<24 0>, <25 0>,
+				<26 0>, <27 0>,
+				<28 0>, <29 0>,
+				<30 0>, <31 0>;
+			#dma-cells = <2>;
+			nxp,version = <5>;
+			dma-channels = <64>;
+			dma-requests = <123>;
+			no-error-irq;
+			status = "disabled";
+		};
+
 		lpuart3: serial@42570000 {
 			compatible = "nxp,imx-lpuart", "nxp,lpuart";
 			reg = <0x42570000 DT_SIZE_K(64)>;
@@ -182,6 +210,8 @@
 			reg = <0x426a0000 DT_SIZE_K(64)>;
 			interrupts = <79 3>;
 			clocks = <&scmi_clk IMX943_CLK_LPUART8>;
+			dmas = <&edma4 0 38>, <&edma4 1 39>;
+			dma-names = "tx", "rx";
 			status = "disabled";
 		};
 
@@ -399,6 +429,62 @@
 			#mbox-cells = <1>;
 		};
 
+		irqsteer: interrupt-controller@44760000 {
+			compatible = "nxp,irqsteer-intc";
+			#size-cells = <0>;
+			#address-cells = <1>;
+			nxp,version = <1>;
+			reg = <0 DT_SIZE_K(1)>;
+
+			irqsteer_master0: interrupt-controller@0 {
+				compatible = "nxp,irqsteer-master";
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts-extended = <&nvic 224 0>;
+			};
+
+			irqsteer_master1: interrupt-controller@1 {
+				compatible = "nxp,irqsteer-master";
+				reg = <1>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts-extended = <&nvic 225 0>;
+			};
+
+			irqsteer_master2: interrupt-controller@2 {
+				compatible = "nxp,irqsteer-master";
+				reg = <2>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts-extended = <&nvic 226 0>;
+			};
+
+			irqsteer_master3: interrupt-controller@3 {
+				compatible = "nxp,irqsteer-master";
+				reg = <3>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts-extended = <&nvic 227 0>;
+			};
+
+			irqsteer_master4: interrupt-controller@4 {
+				compatible = "nxp,irqsteer-master";
+				reg = <4>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts-extended = <&nvic 228 0>;
+			};
+
+			irqsteer_master5: interrupt-controller@5 {
+				compatible = "nxp,irqsteer-master";
+				reg = <5>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts-extended = <&nvic 229 0>;
+			};
+		};
+
 		gpio1: gpio@47400000 {
 			compatible = "nxp,imx-rgpio";
 			reg = <0x47400000 DT_SIZE_K(64)>;

dts/arm/nxp/nxp_imx95_m7.dtsi

@@ -546,7 +546,7 @@
 				compatible = "nxp,irqsteer-master";
 				reg = <0>;
 				interrupt-controller;
-				#interrupt-cells = <1>;
+				#interrupt-cells = <2>;
 				interrupts-extended = <&nvic 224 0>;
 			};
 		};
@@ -564,7 +564,7 @@
 			netc: ethernet {
 				compatible = "nxp,imx-netc";
 				interrupt-parent = <&irqsteer_master0>;
-				interrupts = <13 0 0>;
+				interrupts = <13 0>;
 				#address-cells = <1>;
 				#size-cells = <1>;
 				ranges;

dts/bindings/interrupt-controller/nxp,irqsteer-intc.yaml

@@ -7,3 +7,8 @@ include: [base.yaml]
 properties:
   reg:
     required: true
+
+  nxp,version:
+    type: int
+    description: |
+      MCUX SDK IRQSTEER driver version.

dts/bindings/interrupt-controller/nxp,irqsteer-master.yaml

@@ -6,10 +6,11 @@ include: [interrupt-controller.yaml, base.yaml]
 
 properties:
   "#interrupt-cells":
-    const: 1
+    const: 2
 
   reg:
     required: true
 
 interrupt-cells:
   - irq
+  - priority

dts/xtensa/nxp/nxp_imx8.dtsi

@@ -133,8 +133,8 @@
 		valid-channels = <6>, <7>, <14>, <15>;
 		power-domains = <&edma0_ch6_pd>, <&edma0_ch7_pd>,
 				<&edma0_ch14_pd>, <&edma0_ch15_pd>;
-		interrupts-extended = <&master6 58>, <&master6 58>,
-				      <&master5 29>, <&master5 29>;
+		interrupts-extended = <&master6 58 0>, <&master6 58 0>,
+				<&master5 29 0>, <&master5 29 0>;
 		#dma-cells = <2>;
 		status = "disabled";
 	};
@@ -143,7 +143,7 @@
 		compatible = "nxp,dai-sai";
 		reg = <0x59050000 DT_SIZE_K(64)>;
 		interrupt-parent = <&master5>;
-		interrupts = <28>;
+		interrupts = <28 0>;
 		clocks = <&ccm IMX_CCM_SAI1_CLK 0x0 0x0>;
 		clock-names = "bus";
 		dai-index = <1>;
@@ -177,7 +177,7 @@
 		compatible = "nxp,imx-lpuart", "nxp,lpuart";
 		reg = <0x5a080000 DT_SIZE_K(4)>;
 		interrupt-parent = <&master4>;
-		interrupts = <3>;
+		interrupts = <3 0>;
 		/* this is actually LPUART2 clock but the macro indexing starts at 1 */
 		clocks = <&ccm IMX_CCM_LPUART3_CLK 0x0 0x0>;
 		status = "disabled";

dts/xtensa/nxp/nxp_imx8m.dtsi

@@ -60,23 +60,23 @@
 				compatible = "nxp,irqsteer-master";
 				reg = <0>;
 				interrupt-controller;
-				#interrupt-cells = <1>;
+				#interrupt-cells = <2>;
 				interrupts-extended = <&clic 19 0 0>;
 			};
 
 			master1: interrupt-controller@1 {
 				compatible = "nxp,irqsteer-master";
 				reg = <1>;
 				interrupt-controller;
-				#interrupt-cells = <1>;
+				#interrupt-cells = <2>;
 				interrupts-extended = <&clic 20 0 0>;
 			};
 
 			master2: interrupt-controller@2 {
 				compatible = "nxp,irqsteer-master";
 				reg = <2>;
 				interrupt-controller;
-				#interrupt-cells = <1>;
+				#interrupt-cells = <2>;
 				interrupts-extended = <&clic 21 0 0>;
 			};
 		};
@@ -91,7 +91,7 @@
 			compatible = "nxp,sdma";
 			reg = <0x30e00000 DT_SIZE_K(64)>;
 			interrupt-parent = <&master1>;
-			interrupts = <2 0 0>;
+			interrupts = <2 0>;
 			#dma-cells = <2>;
 			status = "disabled";
 		};
@@ -105,7 +105,7 @@
 			clock-names = "mclk1";
 
 			interrupt-parent = <&master1>;
-			interrupts = <18>;
+			interrupts = <18 0>;
 			dai-index = <3>;
 			/* DMA event source, peripheral type */
 			dmas = <&sdma3 5 5>, <&sdma3 4 5>;
@@ -144,7 +144,7 @@
 			 * until we can support UART interrupts
 			 */
 			interrupt-parent = <&master0>;
-			interrupts = <29 0 0>;
+			interrupts = <29 0>;
 			clocks = <&ccm IMX_CCM_UART4_CLK 0x6c 24>;
 			status = "disabled";
 		};