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stm32n6: Fix xspi devices configuration #95153

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Merged
merged 2 commits into from
Sep 2, 2025
+16 −19
Merged

stm32n6: Fix xspi devices configuration #95153

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5585a25
boards: stm32n6570_dk/nucleo_n657x0_q: Set NOR XSPI controller clk to…
erwango Aug 29, 2025
b209c6d
drivers: flash_stm32_xspi: Fix Dummy Cycles on MX66UM1G45G NOR at 200MHz
erwango Aug 29, 2025
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8 changes: 1 addition & 7 deletions boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -97,12 +97,6 @@
status = "okay";
};

&ic3 {
pll-src = <1>;
ic-div = <6>;
status = "okay";
};

&ic6 {
pll-src = <3>;
ic-div = <2>;
Expand Down Expand Up @@ -231,7 +225,7 @@ zephyr_udc0: &usbotg_hs1 {
&xspim_p2_io6_pn10 &xspim_p2_io7_pn11>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK(AHB5, 12)>,
<&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
<&rcc STM32_SRC_HCLK5 XSPI2_SEL(0)>,
<&rcc STM32_CLOCK(AHB5, 13)>;
status = "okay";

Expand Down
8 changes: 1 addition & 7 deletions boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -144,12 +144,6 @@
status = "okay";
};

&ic3 {
pll-src = <1>;
ic-div = <6>;
status = "okay";
};

&ic4 {
pll-src = <2>;
ic-div = <32>;
Expand Down Expand Up @@ -342,7 +336,7 @@ zephyr_udc0: &usbotg_hs1 {
&xspim_p2_io6_pn10 &xspim_p2_io7_pn11>;
pinctrl-names = "default";
clocks = <&rcc STM32_CLOCK(AHB5, 12)>,
<&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
<&rcc STM32_SRC_HCLK5 XSPI2_SEL(0)>,
<&rcc STM32_CLOCK(AHB5, 13)>;
status = "okay";

Expand Down
19 changes: 14 additions & 5 deletions drivers/flash/flash_stm32_xspi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -568,11 +568,20 @@ static int stm32_xspi_write_enable(const struct device *dev,
}

/* Write Flash configuration register 2 with new dummy cycles */
static int stm32_xspi_write_cfg2reg_dummy(XSPI_HandleTypeDef *hxspi,
static int stm32_xspi_write_cfg2reg_dummy(const struct device *dev,
uint8_t nor_mode, uint8_t nor_rate)
{
uint8_t transmit_data = SPI_NOR_CR2_DUMMY_CYCLES_66MHZ;
XSPI_RegularCmdTypeDef s_command = xspi_prepare_cmd(nor_mode, nor_rate);
const struct flash_stm32_xspi_config *dev_cfg = dev->config;
struct flash_stm32_xspi_data *dev_data = dev->data;
uint8_t transmit_data;

if (dev_cfg->max_frequency == MHZ(200)) {
/* Use memory default value */
return 0;
}
Comment on lines +579 to +582
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Is this a N6-specific hack? If so, a if (IS_ENABLED(CONFIG_SOC_SERIES_STM32N6X) should be added

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@erwango erwango Sep 1, 2025 •
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This configuration is related to the specific NOR device, not the SoC.
As mentioned in the commit description, this fix is definitely not ideal, but these flash drivers are not designed to take into account devices specifics, so I'm minimizing the impact.
In its current shape, this piece code is not correct for some of the configuration that are already in tree, but no issue were reported, so I prefer not touch it more.
A proper change would require to have knowledge about the memory type and implement the full table for each device. In the end what we need is a proper split between devices and controllers ... which will come with MSPI drivers. It would not be duplicated work to start this task on this driver.
Not satisfying but more reasonable from my point of view.


transmit_data = SPI_NOR_CR2_DUMMY_CYCLES_66MHZ;

/* Initialize the writing of configuration register 2 */
s_command.Instruction = (nor_mode == XSPI_SPI_MODE)
Expand All @@ -583,13 +592,13 @@ static int stm32_xspi_write_cfg2reg_dummy(XSPI_HandleTypeDef *hxspi,
s_command.DataLength = (nor_mode == XSPI_SPI_MODE) ? 1U
: ((nor_rate == XSPI_DTR_TRANSFER) ? 2U : 1U);

if (HAL_XSPI_Command(hxspi, &s_command,
if (HAL_XSPI_Command(&dev_data->hxspi, &s_command,
HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
LOG_ERR("XSPI transmit cmd");
return -EIO;
}

if (HAL_XSPI_Transmit(hxspi, &transmit_data,
if (HAL_XSPI_Transmit(&dev_data->hxspi, &transmit_data,
HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
LOG_ERR("XSPI transmit ");
return -EIO;
Expand Down Expand Up @@ -683,7 +692,7 @@ static int stm32_xspi_config_mem(const struct device *dev)
}

/* Write Configuration register 2 (with new dummy cycles) */
if (stm32_xspi_write_cfg2reg_dummy(&dev_data->hxspi,
if (stm32_xspi_write_cfg2reg_dummy(dev,
XSPI_SPI_MODE, XSPI_STR_TRANSFER) != 0) {
LOG_ERR("XSPI write CFGR2 failed");
return -EIO;
Expand Down
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