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drivers: dma: microchip: Introduce G1 DMA Driver #96300
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Add the device tree node and the binding file for microchip dma G1 Peripheral. Signed-off-by: Arunprasath P <[email protected]>
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A good number of things I see that need sorting out, might see some more things once the noise is cut down a bit. If you are using an LLM to generate some stuff, I recommend not doing so (it appears like you might, as there's a lot of redundent commentary in my opinion).
drivers/dma/dma_mchp_dmac_g1.c
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* | ||
* Represents the different states a DMA channel can be in during its lifecycle. | ||
*/ | ||
typedef enum dma_mchp_ch_state { |
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no need to typedef this enum
drivers/dma/dma_mchp_dmac_g1.c
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* This enumeration defines the possible interrupt status codes | ||
* that indicate the outcome of a DMA transaction. | ||
*/ | ||
typedef enum { |
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no need to typedef this enum
drivers/dma/dma_mchp_dmac_g1.c
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* This enumeration defines attribute types that describe hardware-specific | ||
* constraints and capabilities for DMA transfers. | ||
*/ | ||
typedef enum dma_mchp_attribute_type { |
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I'm seeing a pattern, but yeah like the others, don't typedef enums/structs please. We somewhat follow linux coding style and typedefs like this aren't warranted.
https://kernel.org/doc/html/latest/process/coding-style.html#typedefs
drivers/dma/dma_mchp_dmac_g1.c
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{ | ||
dmac_reg->DMAC_CTRL |= DMAC_CTRL_DMAENABLE(0); | ||
dmac_reg->DMAC_CTRL |= DMAC_CTRL_SWRST_Msk; | ||
while ((dmac_reg->DMAC_CTRL & DMAC_CTRL_SWRST_Msk) >> DMAC_CTRL_SWRST_Pos) { |
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use the WAIT_FOR macro here with a time limit if the hardware has some guarantees on time to reset you can follow and fail on
drivers/dma/dma_mchp_dmac_g1.c
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* @param dmac_reg Pointer to the base address of the DMAC peripheral registers. | ||
* @param enable Boolean value to enable (true) or disable (false) the DMA controller. | ||
*/ | ||
static inline void dmac_enable(dmac_registers_t *dmac_reg, bool enable) |
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Recommend a dmac_enable/dmac_disable pair instead of a bool param here
drivers/dma/dma_mchp_dmac_g1.c
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ret = 0; | ||
} while (0); | ||
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if (irq_locked == true) { |
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not needed if you use goto and labels or early returns, please fix and drop do { } while(0);
dma_mchp_channel_config_t *dma_channel_config; | ||
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/* Pool of descriptor */ | ||
struct k_fifo dma_desc_pool; |
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k_fifo really isn't the right tool for this, either use a k_mem_slab, sys_block, or array with atomic bitmap signaling used/unused. If you want the cheapest computational route make an array of arrays, one array for each channel with some number of descriptors. No locks, no lists, no checks needed at all since channels are single owner.
drivers/dma/dma_mchp_dmac_g1.c
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/******************************************* | ||
* @brief Devicetree definitions | ||
*******************************************/ |
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Really not needing to be doc commented here, this is a private file, no doc comments will result in doxygen generation, but its nice to see a consistent style.
Regardless large comment blocks like this aren't needed, everyone in zephyr knows what the DT_DRV_COMPAT is for
drivers/dma/dma_mchp_dmac_g1.c
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*******************************************/ | ||
#define DT_DRV_COMPAT microchip_dmac_g1_dma | ||
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/******************************************* |
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no need to add large comments splitting up sections of the C file like this
* This macro defines the required alignment (in bytes) for the starting address | ||
* of a DMA buffer. For 32-bit transfers, a 4-byte alignment is required. | ||
*/ | ||
#define DMAC_BUF_ADDR_ALIGNMENT 4 |
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Honestly the define is pretty self documented, simple
/* Address alignment for DMA buffers */
Is plenty here, no need to go to length details like this, its just adding line noise.
Same for other defines in the file.
Add DMA driver for Microchip DMA G1 IP Peripherals. Signed-off-by: Arunprasath P <[email protected]>
Update sam_e54_xpro.yml to include DMA in the supported features list. Signed-off-by: Arunprasath P <[email protected]>
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This pull request adds DMA driver support for the Microchip DMAC peripheral. It introduces the DMA driver implementation and updates the devicetree for the SAM D5x/E5x series to include the required node and bindings.