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[FAQ] Which branch should I use?
#4556 · NewPaulWalker opened on Apr 14, 2025
1
Possible bug in statistical corrector
#4242 · castleberrysam opened on Feb 2, 2025
11

[Bug] StoreQueue forwards stale data past a younger store made through a virtual-address synonym
OpenXiangShan/XiangShan#6690 · opened on Oct 8, 2026
1
ColdDownThreshold = 0 silently disables load replay and commits incorrect load data
OpenXiangShan/XiangShan#6688 · opened on Oct 8, 2026
2
vl free list skips an entry when the VTypeBuffer walk ends before the RAB walk, leading to a wrong vl
OpenXiangShan/XiangShan#6684 · opened on Oct 8, 2026
1
PMA non-cacheable DRAM access is issued as a CHI Device transaction and aborts in the memory NCB
OpenXiangShan/XiangShan#6683 · opened on Oct 8, 2026
1
Cross-page HLV.D reports the upper half guest-page fault as a load page fault at the starting address
OpenXiangShan/XiangShan#6682 · opened on Oct 8, 2026
1
Address-specific hfence.gvma leaves the G-stage non-leaf page-table cache valid
OpenXiangShan/XiangShan#6681 · opened on Oct 8, 2026
1
csrr vl right after vsetvli reads 0
OpenXiangShan/XiangShan#6676 · opened on Oct 6, 2026
1
Software prefetch.i stops the simulation: ICacheMetaArray assertion "2 read setIdx must be in the different interleaved bank!"
OpenXiangShan/XiangShan#6674 · opened on Oct 5, 2026
5
After csrw vstart with a nonzero value, the vector instruction right after a vsetvli raises an illegal-instruction exception
OpenXiangShan/XiangShan#6673 · opened on Oct 5, 2026
1
HS-level mstatus.MXR lets the VS-stage page-table walk read a G-stage execute-only page
OpenXiangShan/XiangShan#6672 · opened on Oct 5, 2026
1
mnret raises an illegal-instruction exception in M-mode although the Smrnmi CSRs are implemented
OpenXiangShan/XiangShan#6671 · opened on Oct 5, 2026
2
Leaf PTE with PPN bits above the physical address width: access fault reported where the permission check must raise a page fault
OpenXiangShan/XiangShan#6670 · opened on Oct 5, 2026
1
Leaf PTE with PPN bits above the physical address width is used at the truncated address, without an access fault, after accesses through the other PTEs of its 8-PTE block
OpenXiangShan/XiangShan#6669 · opened on Oct 5, 2026
1
csrr x0, vl / csrr x0, vlenb renames x0: "rfWen cannot be 1 when Int regfile ldest is 0" and "pdest for $0 should be 0"
OpenXiangShan/XiangShan#6668 · opened on Oct 5, 2026
1
cbo.inval zeroes the cache block when xenvcfg.CBIE = 01 turns it into a flush
OpenXiangShan/XiangShan#6666 · opened on Oct 3, 2026
1
Invalid PTE with G=1 is cached as a global PTE
OpenXiangShan/XiangShan#6661 · opened on Oct 1, 2026
1
Vector loads and stores ignore vl, vstart, stride and LMUL
OpenXiangShan/XiangShan#6659 · opened on Sep 30, 2026
1
vslideup.vi blocks the system
OpenXiangShan/XiangShan#6658 · opened on Sep 30, 2026
1
A vector integer divide squashed by a redirect blocks the next divide on VFEX1
OpenXiangShan/XiangShan#6656 · opened on Sep 30, 2026
1
Legal vsse32.v to aligned ordinary RAM stops all commits on kunminghu-v3
OpenXiangShan/XiangShan#6655 · opened on Sep 30, 2026
1
[Bug] zama16b is declared, but misaligned AMOs within a 16-byte granule still trap
OpenXiangShan/XiangShan#6654 · opened on Sep 29, 2026
2
[Bug Report] vmacc/vmadd/vnmsac/vnmsub discard the accumulator under ta
OpenXiangShan/XiangShan#6650 · opened on Sep 29, 2026
1
vfredusum.vs is accepted without an IQ selection and triggers the no-commit watchdog
OpenXiangShan/XiangShan#6644 · opened on Sep 27, 2026
1
vfmv.f.s commits an incorrect FP value despite a correctly boxed FU result
OpenXiangShan/XiangShan#6643 · opened on Sep 27, 2026
1
vfadd.vf treats a non-NaN-boxed FP32 scalar as an ordinary number
OpenXiangShan/XiangShan#6642 · opened on Sep 27, 2026
1

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[Bug] StoreQueue forwards stale data past a younger store made through a virtual-address synonym

`ColdDownThreshold = 0` silently disables load replay and commits incorrect load data

vl free list skips an entry when the VTypeBuffer walk ends before the RAB walk, leading to a wrong vl

PMA non-cacheable DRAM access is issued as a CHI Device transaction and aborts in the memory NCB

Cross-page HLV.D reports the upper half guest-page fault as a load page fault at the starting address

Address-specific hfence.gvma leaves the G-stage non-leaf page-table cache valid

`csrr vl` right after `vsetvli` reads 0

Software `prefetch.i` stops the simulation: ICacheMetaArray assertion "2 read setIdx must be in the different interleaved bank!"

After `csrw vstart` with a nonzero value, the vector instruction right after a `vsetvli` raises an illegal-instruction exception

HS-level `mstatus.MXR` lets the VS-stage page-table walk read a G-stage execute-only page

`mnret` raises an illegal-instruction exception in M-mode although the Smrnmi CSRs are implemented

Leaf PTE with PPN bits above the physical address width: access fault reported where the permission check must raise a page fault

Leaf PTE with PPN bits above the physical address width is used at the truncated address, without an access fault, after accesses through the other PTEs of its 8-PTE block

`csrr x0, vl` / `csrr x0, vlenb` renames x0: "rfWen cannot be 1 when Int regfile ldest is 0" and "pdest for $0 should be 0"

`cbo.inval` zeroes the cache block when `xenvcfg.CBIE` = 01 turns it into a flush

Invalid PTE with G=1 is cached as a global PTE

Vector loads and stores ignore `vl`, `vstart`, stride and LMUL

`vslideup.vi` blocks the system

A vector integer divide squashed by a redirect blocks the next divide on VFEX1

Legal `vsse32.v` to aligned ordinary RAM stops all commits on kunminghu-v3

[Bug] zama16b is declared, but misaligned AMOs within a 16-byte granule still trap

[Bug Report] `vmacc`/`vmadd`/`vnmsac`/`vnmsub` discard the accumulator under `ta`

vfredusum.vs is accepted without an IQ selection and triggers the no-commit watchdog

vfmv.f.s commits an incorrect FP value despite a correctly boxed FU result

vfadd.vf treats a non-NaN-boxed FP32 scalar as an ordinary number