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Pull requests: OpenXiangShan/XiangShan

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Pull requests list

refactor(tage): add BaseTableAlignBank wrapper module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: code quality To make code more readable & maintainable topic: performance To improve performance
#5162 opened Oct 31, 2025 by ngc7331 • Draft kmh-v3
1
fix(abtb): fix condition of writing new entry to abtb module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: funtionality To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5160 opened Oct 31, 2025 by Gao-Zeyu Loading… kmh-v3
2
refactor(mbtb): re-structure code module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: code quality To make code more readable & maintainable topic: funtionality To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5159 opened Oct 30, 2025 by ngc7331 • Draft kmh-v3
1
feat(ubtb): remove takenCnt & valid field module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: area To reduce area comsuption topic: performance To improve performance
#5157 opened Oct 30, 2025 by ngc7331 Loading… kmh-v3
2
fix(Tage): fix tage tagged table performance module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: funtionality To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5156 opened Oct 30, 2025 by TheKiteRunner24 • Draft kmh-v3
fix(Tage,mbtb): fix next set idx logic module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: funtionality To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5155 opened Oct 30, 2025 by TheKiteRunner24 Loading… kmh-v3
1
perf: add perfevent in L2, update Paramters
#5154 opened Oct 29, 2025 by Yan-Yiming Loading…
timing(LoadMisalignBuffer): remove critical path from ECC
#5152 opened Oct 29, 2025 by linjuanZ Loading…
1
feat(sc): add globalTable and ghr module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: funtionality To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5150 opened Oct 29, 2025 by sleep-zzz Loading… kmh-v3
2
fix(resolve): flush branches that are not flushed by backend redirect module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: funtionality To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5149 opened Oct 29, 2025 by Yan-Muzi Loading… kmh-v3
1
feat(Bpu,Ftq): bpu train use DecoupledIO module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: funtionality To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5148 opened Oct 29, 2025 by TheKiteRunner24 Loading… kmh-v3
2
feat(debug): add mstatus in xstop
#5146 opened Oct 28, 2025 by wissygh • Draft
1
perf(ubtb): use fast train by default module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: performance To improve performance
#5145 opened Oct 28, 2025 by ngc7331 Loading… kmh-v3
2
fix(vialuf): refactor vialuf to support fast wakeup module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: funtionality To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5136 opened Oct 22, 2025 by sinceforYy Loading… kmh-v3
chore(backend): improve code quality module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: code quality To make code more readable & maintainable
#5135 opened Oct 22, 2025 by xiaofeibao-xjtu Loading… kmh-v3
1
fix(csr): fix csr out-of-order read xip registers
#5131 opened Oct 20, 2025 by sinceforYy Loading… kmh-v2r2
1
1
bump CoupledL2
#5111 opened Oct 14, 2025 by yulightenyu Loading…
fix(CSR, NMI): fix the logic for gating nmi module: backend Decode, Rename, Issue, Dispatch, Rob, Alu, Csr, fudian, yunsuan topic: funtionality To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5067 opened Sep 25, 2025 by sinceforYy Loading… kmh-v3
1
feat(abtb): support fast predict when s3 override module: frontend Bpu, Ftq, Ifu, ICache, IBuffer topic: performance To improve performance
#5061 opened Sep 24, 2025 by TheKiteRunner24 • Draft kmh-v3
citest
#5051 opened Sep 22, 2025 by xiaofeibao-xjtu • Draft
perf(pf): add berti prefetch module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: performance To improve performance
#5049 opened Sep 21, 2025 by Maxpicca-Li Loading… kmh-v3
3
Uart16550 intgration
#5047 opened Sep 20, 2025 by ARN1954 • Draft
@cebarobot
fix(LoadUnit): tlb.req.kill is only valid when s1_valid module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: funtionality To introduce new function, e.g. new isa extension, bug fix, etc.. Or, to fix bug
#5039 opened Sep 18, 2025 by Anzooooo Loading… kmh-v2r2
timing(LoadQueueReplay): move needReplay generation to LDU module: memory Memblock, DCache, TLB, Prefetcher, coupledL2, huancun topic: timing To fix bad timing
#5029 opened Sep 16, 2025 by jin120811 • Draft
5
feat(pdb): add asm and dasm commands for XSPdb module: tool difftest, gsim, XSpdb, Makefiles, scripts, etc.
#5011 opened Sep 8, 2025 by SFangYy Loading…
2
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