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1.2.3
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@shtaxxx shtaxxx released this 27 Oct 08:10
· 861 commits to master since this release
1.2.3
d6d7478

Update

  • veriloggen/thread/axi.py: A bug fix of the hung up bug of DMA read/write with a wider AXI data width and odd DMA size.
  • README.rst: A bug fix of syntax error.

Test environment

Mac OSX 10.14

  • Python 3.7.0
  • Icarus Verilog 10.2
  • Pyverilog 1.1.2
  • IPgen 1.0.0

Ubuntu 18.04.1

  • Python 3.6.6
  • Icarus Verilog 10.1
  • Pyverilog 1.1.2
  • IPgen 1.0.0
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