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Update utility cores to inline hdl variants (Vivado 2024.2+) #1874

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4 changes: 2 additions & 2 deletions library/axi_tdd/scripts/axi_tdd.tcl
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -42,7 +42,7 @@ proc ad_tdd_gen_create {ip_name
]

for {set i 0} {$i < $num_of_channels} {incr i} {
ad_ip_instance xlslice "${ip_name}/tdd_ch_slice_${i}" [list \
ad_ip_instance ilslice "${ip_name}/tdd_ch_slice_${i}" [list \
DIN_WIDTH $num_of_channels \
DIN_FROM $i \
DIN_TO $i \
Expand Down
18 changes: 8 additions & 10 deletions library/jesd204/scripts/jesd204.tcl
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2017-2022 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2017-2022, 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIJESD204
###############################################################################

Expand Down Expand Up @@ -226,24 +226,24 @@ proc adi_tpl_jesd204_tx_create {ip_name num_of_lanes num_of_converters samples_p
# Concatenation and slicer cores
# xconcat limited to 32 input ports
for {set i 0} {$i < $num_of_converters} {incr i 32} {
ad_ip_instance xlconcat "${ip_name}/data_concat[expr $i/32]" [list \
ad_ip_instance ilconcat "${ip_name}/data_concat[expr $i/32]" [list \
NUM_PORTS [expr min(32,$num_of_converters-$i)] \
]
}
# main concat
if {$num_of_converters > 32} {
ad_ip_instance xlconcat "${ip_name}/data_concat" [list \
ad_ip_instance ilconcat "${ip_name}/data_concat" [list \
NUM_PORTS [expr int(ceil(double($num_of_converters)/32))] \
]
}

for {set i 0} {$i < $num_of_converters} {incr i} {
ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
ad_ip_instance ilslice "${ip_name}/enable_slice_${i}" [list \
DIN_WIDTH $num_of_converters \
DIN_FROM $i \
DIN_TO $i \
]
ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
ad_ip_instance ilslice "${ip_name}/valid_slice_${i}" [list \
DIN_WIDTH $num_of_converters \
DIN_FROM $i \
DIN_TO $i \
Expand Down Expand Up @@ -357,18 +357,18 @@ proc adi_tpl_jesd204_rx_create {ip_name num_of_lanes num_of_converters samples_p
if {$num_of_converters > 1} {
# Slicer cores
for {set i 0} {$i < $num_of_converters} {incr i} {
ad_ip_instance xlslice ${ip_name}/data_slice_$i [list \
ad_ip_instance ilslice ${ip_name}/data_slice_$i [list \
DIN_WIDTH [expr $dma_sample_width*$samples_per_channel*$num_of_converters] \
DIN_FROM [expr $dma_sample_width*$samples_per_channel*($i+1)-1] \
DIN_TO [expr $dma_sample_width*$samples_per_channel*$i] \
]

ad_ip_instance xlslice "${ip_name}/enable_slice_${i}" [list \
ad_ip_instance ilslice "${ip_name}/enable_slice_${i}" [list \
DIN_WIDTH $num_of_converters \
DIN_FROM $i \
DIN_TO $i \
]
ad_ip_instance xlslice "${ip_name}/valid_slice_${i}" [list \
ad_ip_instance ilslice "${ip_name}/valid_slice_${i}" [list \
DIN_WIDTH $num_of_converters \
DIN_FROM $i \
DIN_TO $i \
Expand Down Expand Up @@ -449,5 +449,3 @@ proc adi_jesd204_calc_tpl_width {link_datapath_width jesd_l jesd_m jesd_s jesd_n
}

}


6 changes: 3 additions & 3 deletions projects/ad469x_evb/common/ad469x_bd.tcl
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2020-2024 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2020-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -84,11 +84,11 @@ ad_connect spi_clk $hier_spi_engine/spi_clk
ad_connect $hier_spi_engine/m_spi ad469x_spi
ad_connect axi_ad469x_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE

ad_ip_instance util_vector_logic cnv_gate
ad_ip_instance ilvector_logic cnv_gate
ad_ip_parameter cnv_gate CONFIG.C_SIZE 1
ad_ip_parameter cnv_gate CONFIG.C_OPERATION {and}

ad_ip_instance util_vector_logic cnv_gate_gpio
ad_ip_instance ilvector_logic cnv_gate_gpio
ad_ip_parameter cnv_gate_gpio CONFIG.C_SIZE 1
ad_ip_parameter cnv_gate_gpio CONFIG.C_OPERATION {or}

Expand Down
4 changes: 2 additions & 2 deletions projects/ad738x_fmc/common/ad738x_bd.tcl
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2019-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -51,7 +51,7 @@ ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8
ad_connect $sys_cpu_clk spi_clkgen/clk
ad_connect spi_clk spi_clkgen/clk_0

ad_ip_instance util_vector_logic cnv_gate
ad_ip_instance ilvector_logic cnv_gate
ad_ip_parameter cnv_gate CONFIG.C_SIZE 1
ad_ip_parameter cnv_gate CONFIG.C_OPERATION {and}

Expand Down
12 changes: 6 additions & 6 deletions projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl
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Expand Up @@ -614,7 +614,7 @@ if {$INTF_CFG != "TX"} {
ad_connect ext_sync_in rx_mxfe_tpl_core/adc_tpl_core/adc_sync_in
if {$INTF_CFG == "RXTX"} {
# Rx & Tx
ad_ip_instance util_vector_logic manual_sync_or [list \
ad_ip_instance ilvector_logic manual_sync_or [list \
C_SIZE 1 \
C_OPERATION {or} \
]
Expand All @@ -625,17 +625,17 @@ if {$INTF_CFG != "TX"} {
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_out rx_mxfe_tpl_core/adc_tpl_core/adc_sync_manual_req_in
}
# Reset pack cores
ad_ip_instance util_reduced_logic cpack_rst_logic
ad_ip_instance ilreduced_logic cpack_rst_logic
ad_ip_parameter cpack_rst_logic config.c_operation {or}
ad_ip_parameter cpack_rst_logic config.c_size {3}

ad_ip_instance util_vector_logic rx_do_rstout_logic
ad_ip_instance ilvector_logic rx_do_rstout_logic
ad_ip_parameter rx_do_rstout_logic config.c_operation {not}
ad_ip_parameter rx_do_rstout_logic config.c_size {1}

ad_connect $adc_data_offload_name/s_axis_tready rx_do_rstout_logic/Op1

ad_ip_instance xlconcat cpack_reset_sources
ad_ip_instance ilconcat cpack_reset_sources
ad_ip_parameter cpack_reset_sources config.num_ports {3}
ad_connect rx_device_clk_rstgen/peripheral_reset cpack_reset_sources/in0
ad_connect rx_mxfe_tpl_core/adc_tpl_core/adc_rst cpack_reset_sources/in1
Expand All @@ -657,11 +657,11 @@ if {$INTF_CFG != "RX"} {
ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_out tx_mxfe_tpl_core/dac_tpl_core/dac_sync_manual_req_in
}
# Reset upack cores
ad_ip_instance util_reduced_logic upack_rst_logic
ad_ip_instance ilreduced_logic upack_rst_logic
ad_ip_parameter upack_rst_logic config.c_operation {or}
ad_ip_parameter upack_rst_logic config.c_size {2}

ad_ip_instance xlconcat upack_reset_sources
ad_ip_instance ilconcat upack_reset_sources
ad_ip_parameter upack_reset_sources config.num_ports {2}
ad_connect tx_device_clk_rstgen/peripheral_reset upack_reset_sources/in0
ad_connect tx_mxfe_tpl_core/dac_tpl_core/dac_rst upack_reset_sources/in1
Expand Down
22 changes: 11 additions & 11 deletions projects/ad9081_fmca_ebz/common/versal_transceiver.tcl
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2021-2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -57,11 +57,11 @@ proc create_reset_logic {
set max_lanes [expr max($rx_num_lanes, $tx_num_lanes)]
set num_quads [expr int(ceil(1.0 * $max_lanes / 4))]

ad_ip_instance xlconcat ${ip_name}/concat_powergood [list \
ad_ip_instance ilconcat ${ip_name}/concat_powergood [list \
NUM_PORTS $num_quads \
]

ad_ip_instance util_reduced_logic ${ip_name}/and_powergood [list \
ad_ip_instance ilreduced_logic ${ip_name}/and_powergood [list \
C_SIZE $num_quads \
]

Expand All @@ -87,10 +87,10 @@ proc create_reset_logic {
ad_connect ${ip_name}/${tx_bridge}/gt_ilo_reset ${ip_name}/gt_quad_base_${quad_index}/ch${ch_index}_iloreset
}
}
ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone [list \
ad_ip_instance ilconcat ${ip_name}/xlconcat_iloresetdone [list \
NUM_PORTS ${rx_num_lanes} \
]
ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone [list \
ad_ip_instance ilreduced_logic ${ip_name}/and_iloresetdone [list \
C_SIZE ${rx_num_lanes} \
]
for {set j 0} {$j < ${rx_num_lanes}} {incr j} {
Expand All @@ -101,10 +101,10 @@ proc create_reset_logic {
ad_connect ${ip_name}/xlconcat_iloresetdone/dout ${ip_name}/and_iloresetdone/Op1
ad_connect ${ip_name}/and_iloresetdone/Res ${ip_name}/${rx_bridge}/ilo_resetdone
if {$asymmetric_mode} {
ad_ip_instance xlconcat ${ip_name}/xlconcat_iloresetdone_tx [list \
ad_ip_instance ilconcat ${ip_name}/xlconcat_iloresetdone_tx [list \
NUM_PORTS ${tx_num_lanes} \
]
ad_ip_instance util_reduced_logic ${ip_name}/and_iloresetdone_tx [list \
ad_ip_instance ilreduced_logic ${ip_name}/and_iloresetdone_tx [list \
C_SIZE ${tx_num_lanes} \
]
for {set j 0} {$j < ${tx_num_lanes}} {incr j} {
Expand All @@ -122,10 +122,10 @@ proc create_reset_logic {
}

set num_cplllocks [expr 2 * ${num_quads}]
ad_ip_instance xlconcat ${ip_name}/concat_cplllock [list \
ad_ip_instance ilconcat ${ip_name}/concat_cplllock [list \
NUM_PORTS ${num_cplllocks} \
]
ad_ip_instance util_reduced_logic ${ip_name}/and_cplllock [list \
ad_ip_instance ilreduced_logic ${ip_name}/and_cplllock [list \
C_SIZE ${num_cplllocks} \
]

Expand All @@ -142,7 +142,7 @@ proc create_reset_logic {
ad_connect ${ip_name}/and_cplllock/Res ${ip_name}/${tx_bridge}/gt_lcpll_lock
}

ad_ip_instance xlconcat ${ip_name}/concat_phystatus [list \
ad_ip_instance ilconcat ${ip_name}/concat_phystatus [list \
NUM_PORTS ${rx_num_lanes} \
]
for {set j 0} {$j < ${rx_num_lanes}} {incr j} {
Expand All @@ -153,7 +153,7 @@ proc create_reset_logic {
}
ad_connect ${ip_name}/concat_phystatus/dout ${ip_name}/${rx_bridge}/ch_phystatus_in
if {$asymmetric_mode} {
ad_ip_instance xlconcat ${ip_name}/concat_phystatus_tx [list \
ad_ip_instance ilconcat ${ip_name}/concat_phystatus_tx [list \
NUM_PORTS ${rx_num_lanes} \
]
for {set j 0} {$j < ${rx_num_lanes}} {incr j} {
Expand Down
10 changes: 5 additions & 5 deletions projects/ad9081_fmca_ebz/vcu118/system_bd.tcl
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Expand Up @@ -240,15 +240,15 @@ if {$ad_project_params(CORUNDUM) == "1"} {
ad_connect corundum_hierarchy/input_axis_tdata util_corundum_cpack/packed_fifo_wr_data
ad_connect corundum_hierarchy/input_axis_tready util_corundum_cpack/packed_fifo_wr_overflow

ad_ip_instance util_reduced_logic cpack_rst_logic_corundum
ad_ip_instance ilreduced_logic cpack_rst_logic_corundum
ad_ip_parameter cpack_rst_logic_corundum config.c_operation {or}
ad_ip_parameter cpack_rst_logic_corundum config.c_size {4}

ad_ip_instance util_vector_logic rx_do_rstout_logic_corundum
ad_ip_instance ilvector_logic rx_do_rstout_logic_corundum
ad_ip_parameter rx_do_rstout_logic_corundum config.c_operation {not}
ad_ip_parameter rx_do_rstout_logic_corundum config.c_size {1}

ad_ip_instance xlconcat cpack_reset_sources_corundum
ad_ip_instance ilconcat cpack_reset_sources_corundum
ad_ip_parameter cpack_reset_sources_corundum config.num_ports {4}

ad_connect corundum_hierarchy/input_axis_tready rx_do_rstout_logic_corundum/Op1
Expand All @@ -261,7 +261,7 @@ if {$ad_project_params(CORUNDUM) == "1"} {
ad_connect cpack_reset_sources_corundum/dout cpack_rst_logic_corundum/op1
ad_connect cpack_rst_logic_corundum/res util_corundum_cpack/reset

ad_ip_instance xlconcat input_enable_concat_corundum
ad_ip_instance ilconcat input_enable_concat_corundum
ad_ip_parameter input_enable_concat_corundum config.num_ports $INPUT_CHANNELS

for {set i 0} {$i<$INPUT_CHANNELS} {incr i} {
Expand All @@ -270,7 +270,7 @@ if {$ad_project_params(CORUNDUM) == "1"} {

ad_connect input_enable_concat_corundum/dout corundum_hierarchy/input_enable

ad_ip_instance xlconcat output_enable_concat_corundum
ad_ip_instance ilconcat output_enable_concat_corundum
ad_ip_parameter output_enable_concat_corundum config.num_ports $OUTPUT_CHANNELS

for {set i 0} {$i<$OUTPUT_CHANNELS} {incr i} {
Expand Down
2 changes: 1 addition & 1 deletion projects/ad_gmsl2eth_sl/common/ad_gmsl2eth_sl_bd.tcl
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Expand Up @@ -534,7 +534,7 @@ assign_bd_address -offset 0xA000_0000 [get_bd_addr_segs \
corundum_hierarchy/corundum_core/s_axil_ctrl/Reg
] -target_address_space sys_ps8/Data

ad_ip_instance util_reduced_logic util_reduced_logic_0
ad_ip_instance ilreduced_logic util_reduced_logic_0
ad_ip_parameter util_reduced_logic_0 CONFIG.C_OPERATION {or}
ad_ip_parameter util_reduced_logic_0 CONFIG.C_SIZE {8}

Expand Down
17 changes: 8 additions & 9 deletions projects/ad_quadmxfe1_ebz/common/ad_quadmxfe1_ebz_bd.tcl
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Expand Up @@ -226,11 +226,11 @@ ad_data_offload_create $adc_offload_name \
ad_ip_parameter $adc_offload_name/i_data_offload CONFIG.SYNC_EXT_ADD_INTERNAL_CDC 0
ad_connect $adc_offload_name/sync_ext GND

ad_ip_instance util_vector_logic rx_do_rstout_logic
ad_ip_instance ilvector_logic rx_do_rstout_logic
ad_ip_parameter rx_do_rstout_logic config.c_operation {not}
ad_ip_parameter rx_do_rstout_logic config.c_size {1}

ad_ip_instance util_vector_logic cpack_reset_logic
ad_ip_instance ilvector_logic cpack_reset_logic
ad_ip_parameter cpack_reset_logic config.c_operation {or}
ad_ip_parameter cpack_reset_logic config.c_size {1}

Expand Down Expand Up @@ -477,8 +477,8 @@ ad_connect axi_mxfe_rx_jesd/rx_axi/device_reset jesd204_phy_125_126/rx_reset_gt
#
if {$ADI_PHY_SEL == 0} {
# Rx Physical lanes to PHY
ad_ip_instance xlconcat rx_concat_7_0_p [list NUM_PORTS {8}]
ad_ip_instance xlconcat rx_concat_7_0_n [list NUM_PORTS {8}]
ad_ip_instance ilconcat rx_concat_7_0_p [list NUM_PORTS {8}]
ad_ip_instance ilconcat rx_concat_7_0_n [list NUM_PORTS {8}]

ad_connect rx_data_0_p rx_concat_7_0_p/In0
ad_connect rx_data_1_p rx_concat_7_0_p/In1
Expand All @@ -501,8 +501,8 @@ ad_connect rx_data_7_n rx_concat_7_0_n/In7
ad_connect jesd204_phy_121_122/rxp_in rx_concat_7_0_p/dout
ad_connect jesd204_phy_121_122/rxn_in rx_concat_7_0_n/dout

ad_ip_instance xlconcat rx_concat_15_8_p [list NUM_PORTS {8}]
ad_ip_instance xlconcat rx_concat_15_8_n [list NUM_PORTS {8}]
ad_ip_instance ilconcat rx_concat_15_8_p [list NUM_PORTS {8}]
ad_ip_instance ilconcat rx_concat_15_8_n [list NUM_PORTS {8}]

ad_connect rx_data_8_p rx_concat_15_8_p/In0
ad_connect rx_data_9_p rx_concat_15_8_p/In1
Expand Down Expand Up @@ -604,13 +604,13 @@ if {$ADI_PHY_SEL == 0} {
# Tx Physical lanes to PHY
#
for {set i 0} {$i < $MAX_TX_LANES} {incr i} {
ad_ip_instance xlslice txp_out_slice_$i [list \
ad_ip_instance ilslice txp_out_slice_$i [list \
DIN_TO [expr $i % 8] \
DIN_FROM [expr $i % 8] \
DIN_WIDTH {8} \
DOUT_WIDTH {1} \
]
ad_ip_instance xlslice txn_out_slice_$i [list \
ad_ip_instance ilslice txn_out_slice_$i [list \
DIN_TO [expr $i % 8] \
DIN_FROM [expr $i % 8] \
DIN_WIDTH {8} \
Expand Down Expand Up @@ -740,4 +740,3 @@ ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq
ad_cpu_interrupt ps-11 mb-14 axi_mxfe_rx_jesd/irq
ad_cpu_interrupt ps-10 mb-15 axi_mxfe_tx_jesd/irq
ad_cpu_interrupt ps-14 mb-8 axi_gpio_2/ip2intc_irpt

2 changes: 1 addition & 1 deletion projects/adrv9009/common/adrv9009_bd.tcl
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Expand Up @@ -338,7 +338,7 @@ ad_connect adrv9009_tx_device_clk_rstgen/peripheral_reset util_adrv9009_tx_upac
if {$TX_NUM_OF_CONVERTERS <= 2} {
ad_connect tx_fir_interpolator/valid_out_0 util_adrv9009_tx_upack/fifo_rd_en
} else {
ad_ip_instance util_vector_logic logic_or [list \
ad_ip_instance ilvector_logic logic_or [list \
C_OPERATION {or} \
C_SIZE 1]

Expand Down
4 changes: 2 additions & 2 deletions projects/adrv9009zu11eg/adrv2crr_fmcomms8/system_bd.tcl
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@@ -1,5 +1,5 @@
###############################################################################
## Copyright (C) 2020-2023 Analog Devices, Inc. All rights reserved.
## Copyright (C) 2020-2023, 2025 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

Expand Down Expand Up @@ -32,7 +32,7 @@ create_bd_port -dir I spi1_miso
set_property -dict [list CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {1} CONFIG.PSU__SPI1__PERIPHERAL__IO {EMIO}] [get_bd_cells sys_ps8]
set_property -dict [list CONFIG.PSU__SPI1__GRP_SS1__ENABLE {1} CONFIG.PSU__SPI1__GRP_SS2__ENABLE {1}] [get_bd_cells sys_ps8]

ad_ip_instance xlconcat spi1_csn_concat
ad_ip_instance ilconcat spi1_csn_concat
ad_ip_parameter spi1_csn_concat CONFIG.NUM_PORTS 3
ad_connect sys_ps8/emio_spi1_ss_o_n spi1_csn_concat/In0
ad_connect sys_ps8/emio_spi1_ss1_o_n spi1_csn_concat/In1
Expand Down
2 changes: 1 addition & 1 deletion projects/adrv9009zu11eg/common/adrv2crr_fmc_bd.tcl
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Expand Up @@ -80,7 +80,7 @@ ad_ip_parameter axi_fan_control_0 CONFIG.ID 1
ad_ip_parameter axi_fan_control_0 CONFIG.PWM_FREQUENCY_HZ 1000
ad_ip_parameter axi_fan_control_0 CONFIG.INTERNAL_SYSMONE 1

ad_ip_instance xlconstant const_gnd_0
ad_ip_instance ilconstant const_gnd_0
ad_ip_parameter const_gnd_0 CONFIG.CONST_WIDTH {10}
ad_ip_parameter const_gnd_0 CONFIG.CONST_VAL {0}

Expand Down
6 changes: 3 additions & 3 deletions projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl
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Expand Up @@ -170,7 +170,7 @@ ad_connect gpio_t sys_ps8/emio_gpio_t

# spi

ad_ip_instance xlconcat spi0_csn_concat
ad_ip_instance ilconcat spi0_csn_concat
ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
ad_connect sys_ps8/emio_spi0_ss1_o_n spi0_csn_concat/In1
Expand All @@ -194,10 +194,10 @@ ad_connect sys_cpu_clk rom_sys_0/clk

# interrupts

ad_ip_instance xlconcat sys_concat_intc_0
ad_ip_instance ilconcat sys_concat_intc_0
ad_ip_parameter sys_concat_intc_0 CONFIG.NUM_PORTS 8

ad_ip_instance xlconcat sys_concat_intc_1
ad_ip_instance ilconcat sys_concat_intc_1
ad_ip_parameter sys_concat_intc_1 CONFIG.NUM_PORTS 8

ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
Expand Down
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