v2.2.2

• Introducing the AWS EC2 F2 Runtime AMI Builder (RAB)
  • The RAB is a customizable and extensible tool based on the AWS CDK that easily automates building production-ready AMIs tailored to each accelerator application's needs
  • To get started building a runtime AMI, see the README here
  • Default components are provided to modularly install specific features such as Vivado Lab Edition, the AWS CLI, the AWS FPGA SDK, and more
  • To learn how to integrate the RAB into existing AWS CDK flows, see the code example here
• Updated Rocky FPGA Developer AMI name and description to match Marketplace info
• Added F2 AFI Manifest specification for the version number, ID, and clock parameters
• Added new "--no-encrypt" build option to the HDK flow to facilitate source code debugging
• Updated fpga_clkgen_util and sde_examples with better error handling procedures, addressing stability issues found on Rocky Linux.

v2.2.1

• Release of FPGA Developer AMI 1.18.0 (Rocky Linux 8.10) with Vivado/Vitis 2025.1 tools pre-installed
• Release of Vivado HLx flow
• Fixed TCL glob expression to properly read both .sv and .v files. Credit to @pyz-creeper and @dsw for this update!
• Updated error codes in create-fpga-image for unsupported design logic
• Updated the Virtual Ethernet Application to write the DMA buffer descriptors using the byte alignment required by the CL_SDE example, preventing data alignment errors on Rocky
• Added Amazon FPGA Image (AFI) creation Python script
• Updated XRT version which includes stability fixes for Vitis

v2.2.0

• Release of Vivado/Vitis 2025.1 Tools on FPGA Developer AMI 1.18.0 (Ubuntu)
• Introduced MSI-X PCIe Interrupts Guided Example
• Added Loopback performance test for CL_SDE
• ReadTheDocs navigation improvements

v2.1.2

• Introduced Python Bindings to the SDK
• Added documentation for Python binding usage and setup
• Examples demonstrating Python-based FPGA control
• Added link to instructions for DCV licensing setup. Credit to @morgnza for this update!
• Added verbiage to DCV setup guide to show where to set virtual display resolution
• Fix to Bandwidth Calculation

v2.1.1

• Added global register offset for the SDE IP.
• Added CL_SDE software exmaple for a user allocated DMA buffer.
• Documentation to assist F2 customers with releasing AFIs and AMIs on the AWS Marketplace.
• Documentation to assist in creating a virtual desktop based on the FPGA Developer AMI running graphics-intensive applications remotely on Amazon EC2 instances.
• Fixed the BW calculation and tolerance calculation in the test_hbm_perf_random in the cl_mem_perf.

v2.1.0

Support for Vivado and Vitis 2024.2 tools.
Releasing New Developer AMI for 2024.2 tools.
Updating the asynchronous fpga_mgmt_examples to poll each FPGA once before moving to the next.

v2.0.7

Documentation updates to improve ReadTheDocs navigation and inline snippets.
XSIM template script update to extend the waveform dump time.
Added section with instructions for assigning custom PCIe IDs to HDK README.
Added supplementary XDMA driver installation guide
Updated ERRATA with fix for XSIM when simulating HBM.
Revised the Vitis README with updated code snippets, more detail about the XRT setup, and a new guided example of the Hardware Emulation workflow.
Fixed HDK DCP Tarball path issue described in #706.

v2.0.6

Releasing CL_SDE software examples to demonstrate how to use the Streaming Data Engine (SDE) DMA on small shell.
Fixing the virtual ethernet PacketGen Dual Instance Loopback example to forward packets back to the PacketGen instance.
Fixing DDR backdoor access in simulation.

v2.0.5

• Releasing instructions for using the Vivado GUI.
• Updating virtual_ethernet_install.py to no longer require sudo when run.
• Updating f2_mgmt_example, load_multiple_fpga.c, to load AFIs in parallel.
• Updated ReadTheDocs theme.
• Added the "F2 Software Performance Optimization Guide" with techniques for f2.48xlarge instances

v2.0.4

Release of f2.6xlarge instance size.