[ARM] [IR] [Builtins] Give the data barrier instructions the same attributes they have in AArch64

[AZero13]

They are IntrNoFree and IntrWillReturn, so give them that.

[llvmbot]

@llvm/pr-subscribers-llvm-ir

@llvm/pr-subscribers-backend-arm

Author: AZero13 (AZero13)

Changes

They are IntrNoFree and IntrWillReturn, so give them that.

---

Full diff: https://github.com/llvm/llvm-project/pull/152415.diff

1 Files Affected:

• (modified) llvm/include/llvm/IR/IntrinsicsARM.td (+3-4)

diff --git a/llvm/include/llvm/IR/IntrinsicsARM.td b/llvm/include/llvm/IR/IntrinsicsARM.td
index 1219ce2f86da8..89e412180fc31 100644
--- a/llvm/include/llvm/IR/IntrinsicsARM.td
+++ b/llvm/include/llvm/IR/IntrinsicsARM.td
@@ -299,13 +299,12 @@ def int_arm_ldaexd : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_ptr_ty]>;
 //===----------------------------------------------------------------------===//
 // Data barrier instructions
 
-// TODO: Add applicable default attributes.
 def int_arm_dmb : ClangBuiltin<"__builtin_arm_dmb">, MSBuiltin<"__dmb">,
-                  Intrinsic<[], [llvm_i32_ty]>;
+                  Intrinsic<[], [llvm_i32_ty], [IntrNoFree, IntrWillReturn]>;
 def int_arm_dsb : ClangBuiltin<"__builtin_arm_dsb">, MSBuiltin<"__dsb">,
-                  Intrinsic<[], [llvm_i32_ty]>;
+                  Intrinsic<[], [llvm_i32_ty], [IntrNoFree, IntrWillReturn]>;
 def int_arm_isb : ClangBuiltin<"__builtin_arm_isb">, MSBuiltin<"__isb">,
-                  Intrinsic<[], [llvm_i32_ty]>;
+                  Intrinsic<[], [llvm_i32_ty], [IntrNoFree, IntrWillReturn]>;
 
 //===----------------------------------------------------------------------===//
 // VFP