I$/D$ Cache Line Parametrization Improvements

[davymillion]

Hi all,

I worked recently with your fork of OpenPiton+Sargantana and I ran into some issues when trying to use 32-byte cache lines with the I$. The parametrization is I think incomplete, which led some inconsistencies (for example, for the index size) across the core_tile + sargantana + icache modules.

This PR mainly proposes to fix this. I propose to group all the icache parameters in the sargantana_icache_pkg (some of them were removed from the drac_pkg) and I also propose a simpler interface, similar to the one used in CVA6, where most of the parameters of the icache are computed from the icache size, its number of ways, the cache line size and the sizes of the physical/virtual addresses used. In the process, I removed some duplicated parameters and I had to replace some hardcoded values by package parameters.

I'll open other PRs for the sargantana + icache submodules.

Tell me what you think :)