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I$/D$ Cache Line Parametrization Improvements #8

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3681e6f
Fix parameterization with d/i-cache line size != 64-bytes
davymillion Jul 19, 2025
014a4a8
Update sargantana and icache submodules
davymillion Jul 19, 2025
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2 changes: 1 addition & 1 deletion rtl/core/sargantana
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Submodule sargantana updated 1 files
+0 −8 includes/drac_pkg.sv
22 changes: 11 additions & 11 deletions rtl/drac_openpiton_wrapper.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,8 @@
* Description : Sargantana Wrapper to be used in OpenPiton
* History :
*/

module drac_openpiton_wrapper
import drac_pkg::*; import hpdcache_pkg::*; import wt_cache_pkg::*;
import drac_pkg::*; import sargantana_icache_pkg::*; import hpdcache_pkg::*; import wt_cache_pkg::*;
#(
// IO addresses
parameter int unsigned NIOSections = 1,
Expand Down Expand Up @@ -117,7 +116,7 @@ localparam drac_cfg_t DracOpenPitonCfg = '{

// Memory Interface Config
MemAddrWidth: 40,
MemDataWidth: 512,
MemDataWidth: DCACHE_BUS_WIDTH,
MemIDWidth: 8
};

Expand All @@ -140,13 +139,13 @@ logic [39:0] brom_req_address;
logic brom_req_valid;

// icache wires
logic l1_request_valid;
logic l2_response_valid;
logic [PHY_ADDR_SIZE-1:0] l1_request_paddr;
logic [511:0] l2_response_data; // TODO: LOCALPARAMETERS or PKG definition
logic [1:0] l2_response_seqnum;
logic l2_inval_request;
logic [39:0] l2_inval_addr;
logic l1_request_valid;
logic l2_response_valid;
logic [PHY_ADDR_SIZE-1:0] l1_request_paddr;
logic [ICACHELINE_SIZE-1:0] l2_response_data;
logic [1:0] l2_response_seqnum;
logic l2_inval_request;
logic [39:0] l2_inval_addr;
assign l2_response_seqnum = '0;

// Miss read interface
Expand Down Expand Up @@ -348,7 +347,7 @@ cinco_ranch_hpdcache_subsystem_l15_adapter #(
.DcacheReadPort (DCACHE_READ_PORT),
.DcacheWritePort (DCACHE_WRITE_PORT),
.DcacheAmoPort (DCACHE_AMO_PORT),
.IcacheMemDataWidth (512), //L1I cacheline
.IcacheMemDataWidth (ICACHELINE_SIZE), //L1I cacheline
.IcacheAddrWidth (40),
.HPDcacheMemDataWidth (DracOpenPitonCfg.MemDataWidth), //L1D cacheline
.IcacheNoCachableSize (`MSG_DATA_SIZE_8B), // 8B
Expand All @@ -359,6 +358,7 @@ cinco_ranch_hpdcache_subsystem_l15_adapter #(
.hpdcache_mem_resp_w_t (hpdcache_mem_resp_w_t),
.hpdcache_mem_id_t (hpdcache_mem_id_t),
.hpdcache_mem_addr_t (hpdcache_mem_addr_t),
.hpdcache_nline_t (hpdcache_nline_t),
.req_portid_t (req_portid_t)
) l15_adapter_inst(

Expand Down
2 changes: 1 addition & 1 deletion rtl/icache
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Submodule icache updated 3 files
+48 −30 includes/sargantana_icache_pkg.sv
+15 −22 rtl/sargantana_top_icache.sv
+4 −3 rtl/wrapper_sargantana_top_icache.sv
5 changes: 3 additions & 2 deletions rtl/interface_icache/rtl/icache_interface.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@
module icache_interface
import drac_pkg::*;
import riscv_pkg::*;
import sargantana_icache_pkg::*;
(
input logic clk_i,
input logic rstn_i,
Expand Down Expand Up @@ -59,8 +60,8 @@ assign do_icache_request_int = req_fetch_icache_i.valid &
icache_req_ready_i ;


assign icache_req_bits_vpn_o = req_fetch_icache_i.vaddr[drac_pkg::PHY_VIRT_MAX_ADDR_SIZE-1:12];
assign icache_req_bits_idx_o = req_fetch_icache_i.vaddr[11:0];
assign icache_req_bits_vpn_o = req_fetch_icache_i.vaddr[PHY_VIRT_MAX_ADDR_SIZE-1:ICACHE_INDEX_SIZE];
assign icache_req_bits_idx_o = req_fetch_icache_i.vaddr[ICACHE_INDEX_SIZE-1:0];


assign icache_req_kill_o = req_fetch_icache_i.inval_fetch; // TODO: disabled when is_brom_access??
Expand Down
4 changes: 2 additions & 2 deletions rtl/interface_icache/rtl/nc_icache_buffer.sv
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Expand Up @@ -23,9 +23,9 @@ module nc_icache_buffer
import drac_pkg::*, sargantana_icache_pkg::*;
#(
parameter drac_pkg::drac_cfg_t DRAC_CFG = drac_pkg::DracDefaultConfig,
parameter int unsigned L2_DATA_WIDTH = 512,
parameter int unsigned L2_DATA_WIDTH = ICACHELINE_SIZE,
parameter int unsigned L2_NC_DATA_WIDTH = 64,
parameter int unsigned CORE_DATA_WIDTH = 512
parameter int unsigned CORE_DATA_WIDTH = ICACHELINE_SIZE
) (
input logic clk_i, rstn_i,

Expand Down
3 changes: 2 additions & 1 deletion rtl/openpiton_adapter/rtl/cinco_ranch_hpdcache_subsystem_l15_adapter.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -381,7 +381,8 @@ module cinco_ranch_hpdcache_subsystem_l15_adapter
.WriteByteMaskEnabled (WriteCoalescingEn),
.HPDcacheMemDataWidth (HPDcacheMemDataWidth),
.IcacheNoCachableSize (IcacheNoCachableSize),
.IcacheCachableSize (`MSG_DATA_SIZE_64B), // Hardcoded!!!
.IcacheCachableSize ((IcacheMemDataWidth == 512) ?
`MSG_DATA_SIZE_64B : `MSG_DATA_SIZE_32B),
.hpdcache_mem_req_t (hpdcache_mem_req_t),
.hpdcache_mem_req_w_t (hpdcache_mem_req_w_t),
.hpdcache_mem_id_t (hpdcache_mem_id_t),
Expand Down
2 changes: 1 addition & 1 deletion rtl/sargantana_subtile.sv
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
`include "hpdcache_typedef.svh"

module sargantana_subtile
import drac_pkg::*, sargantana_icache_pkg::*, mmu_pkg::*, hpdcache_pkg::*;
import drac_pkg::*, mmu_pkg::*, hpdcache_pkg::*;
#(
parameter drac_pkg::drac_cfg_t DracCfg = drac_pkg::DracDefaultConfig,

Expand Down
24 changes: 11 additions & 13 deletions rtl/top_tile.sv
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Expand Up @@ -78,11 +78,11 @@ module top_tile
//------------------------------------------------------------------------------------

//- From L2
input logic io_mem_grant_valid,
input logic [511:0] io_mem_grant_bits_data,
input logic [1:0] io_mem_grant_bits_addr_beat,
input logic io_mem_grant_inval,
input logic [11:0] io_mem_grant_inval_addr,
input logic io_mem_grant_valid,
input logic [ICACHELINE_SIZE-1:0] io_mem_grant_bits_data,
input logic [1:0] io_mem_grant_bits_addr_beat,
input logic io_mem_grant_inval,
input logic [11:0] io_mem_grant_inval_addr,


//----------------------------------------------------------------------------------
Expand Down Expand Up @@ -186,11 +186,6 @@ module top_tile

);

// PPN Size is address size - set bits - offset bits
localparam int unsigned ICACHE_NUM_SETS = 64;
localparam int unsigned ICACHE_INDEX_SIZE = $clog2(ICACHE_NUM_SETS) + $clog2(ICACHELINE_SIZE/8);
localparam int unsigned ICACHE_PPN_SIZE = PHY_VIRT_MAX_ADDR_SIZE - ICACHE_INDEX_SIZE;
localparam int unsigned ICACHE_VPN_SIZE = PHY_VIRT_MAX_ADDR_SIZE - ICACHE_INDEX_SIZE;

// *** dCache ***
parameter HPDCACHE_NREQUESTERS = 2; // Core + PTW
Expand Down Expand Up @@ -388,7 +383,9 @@ assign debug_reg_rf_rdata_o = debug_reg_out.rf_rdata;

// *** iCache ***

nc_icache_buffer nc_icache_bf (
nc_icache_buffer #(
.DRAC_CFG (DracCfg)
) nc_icache_bf (
.clk_i,
.rstn_i,

Expand All @@ -415,11 +412,12 @@ sargantana_top_icache # (
.KILL_RESP ( 1'b1 ),
.LINES_256 ( 1'b0 ),

.ICACHE_SIZE (ICACHE_SIZE),
.ICACHE_MEM_BLOCK (ICACHELINE_SIZE/8), // In Bytes
.ASSOCIATIVE (ICACHE_ASSOC),
.PADDR_SIZE (PHY_ADDR_SIZE),
.ADDR_SIZE (PHY_VIRT_MAX_ADDR_SIZE),
.IDX_BITS_SIZE (12), // TODO: Where does this come from?
.FETCH_WIDHT (ICACHELINE_SIZE)
.FETCH_WIDHT (FETCH_WIDHT)
) icache (
`ifdef INTEL_PHYSICAL_MEM_CTRL
.hduspsr_mem_ctrl (hduspsr_mem_ctrl),
Expand Down