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1 change: 1 addition & 0 deletions embassy-stm32/CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- fix: Avoid generating timer update events when updating the frequency ([#4890](https://github.com/embassy-rs/embassy/pull/4890))
- chore: cleanup low-power add time
- fix: Allow setting SAI peripheral `frame_length` to `256`
- fix: stm32/i2c fix busy waiting on BUSY flag in v2
- fix: flash erase on dual-bank STM32Gxxx
- feat: Add support for STM32N657X0
- feat: timer: Add 32-bit timer support to SimplePwm waveform_up method following waveform pattern ([#4717](https://github.com/embassy-rs/embassy/pull/4717))
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6 changes: 0 additions & 6 deletions embassy-stm32/src/i2c/v2.rs
Original file line number Diff line number Diff line change
Expand Up @@ -199,13 +199,7 @@ impl<'d, M: Mode, IM: MasterMode> I2c<'d, M, IM> {
while info.regs.cr2().read().start() {
timeout.check()?;
}

// Wait for the bus to be free
while info.regs.isr().read().busy() {
timeout.check()?;
}
}

// Set START and prepare to send `bytes`. The
// START bit can be set even if the bus is BUSY or
// I2C is in slave mode.
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