ASLRef EAC2 release

This is a snapshot corresponding to the ASLRef EAC2 release.

ArmARM-M.c

This release is based on formal concurrency model released with the Arm ARM issue M.c and includes the following changes to the Arm A-profile A64 Instruction Set Architecture:

• AARCH-25669 Move the ordering rules for LDIAPP/STILP to a new definition
• AARCH-25405 Clarification οf the IC-Coherence-before and Instruction-read-ordered-before definitions
• AARCH-24800 Ordering semantics for Load instructions whose destination register is WZR/XZR

ASLRef EAC1 release

This is a snapshot corresponding to the ASLRef EAC1 release.

ArmARM-M.b

This release is based on formal concurrency model released with the Arm ARM issue M.a and includes the following achritectural changes:

• AARCH-25030 Simplify the definition of Pick Basic Dependency
• AARCH-24667 Explicit-hazard-ordered-before for Hardware Update Effects
• AARCH-24876 Strengthening of the TLBI-ordered-before relation
• AARCH-24989 Remove the MMU Fault Successor from Locally-ordered-before
• AARCH-25105 Ordering implications of a DSB when used to complete a TLBI or an IC
• AARCH-24987 Relax the definition Barrier-ordered-before in relation to Fault Effects
• AARCH-24234 Changes to the shareability domain argument for DMB and DSB instructions

ArmARM-M.a

This release corresponds to the formal memory model that is published with the Arm® Architecture Reference Manual
for A-profile architecture Issue M.a.

ASLRef EAC0 release

This is a snapshot corresponding to the ASLRef EAC0 release.

ASLRef BET2 release

This is a snapshot corresponding to the ASLRef BET2 release.

ASLRef BET1 release

This is a snapshot corresponding to the ASLRef BET1 release.

ASLRef BET0 release

This is a snapshot corresponding to the ASLRef BET0 release.

ASLRef ALP3.1 release

This is a snapshot corresponding to the ASLRef ALP3.1 release.