LOGIC PLAYGROUND

A structured personal repository for FPGA development — covering guides, RTL designs, drivers, mini projects, toolflow, and IP integration built on Xilinx/Vivado with VHDL.

Guides & References

#	Guide	Topic
0	VHDL Template & Syntax Notes	Entity/architecture structure, coding conventions
1	VHDL Notes: Behaviors, Pitfalls, and Useful Tricks	Signal vs variable timing, latch prevention, CDC
2	Peripheral Driver Development Guide	Datasheet → architecture → VHDL → simulation → hardware

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VHDL / RTL Design

#	Project	Key Concept
0	N-Bit Adder with VIO (Cmod A7)	generate loops for parametric design, VIO debugging
1	Button Debouncer — FSM Design & Signal Timing	FSM + timer integration, signal scheduling, metastability from external inputs
2	Button-Selectable Timer & LED Counter	Module cascading, edge detection, clock-derived timing
3	Tick-Based PWM Output Module	Double-buffered duty cycle for glitch-free updates
4	Percentage-based PWM Output	Integer rounding (add-50/divide-100), period-boundary latching
5	UART Transmitter	Bit-timing via counter FSM, shift register TX
6	UART Receiver	Mid-bit sampling (T/2 start, then every T), frame validation
7	BRAM Usage — Single-Port Block RAM	BRAM inference, READ/WRITE_FIRST modes, pipeline latency
8	SPI Master — Mode 0	Timer-based edge detection, deterministic SCK phase
9	SPI Master — All Modes	CPOL/CPHA generics, all 4 SPI modes from one RTL source
10	SPI Master — With CS/Idle Timing	Parameterized CS and IDLE delay times, dead-time enforcement between frames

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Mini Projects

#	Project	Key Concept
0	Sawtooth Wave Generator via PmodDA4	Clock Wizard IP (12→100 MHz), 50 MHz SPI, pipelined waveform generation
1	RGB LED Controller	Three-channel PWM RGB driver, 50% duty cap, combinational color lookup

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IP Cores

#	Project	Key Concept
0	Sine Wave Generation using Xilinx DDS Compiler	Phase accumulator, Frequency Tuning Word calculation

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Drivers

#	Project	Key Concept
0	PmodDA4 Driver — Digilent reference adaptation	SPI frame construction, analog slew rate constraints
1	PmodDA4 Driver — AD5628 with Universal SPI Master	From-scratch FSM over generic SPI IP, INIT_REF sequencing, CS/idle timing constraints

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MicroBlaze (Soft Processor)

#	Project	Key Concept
0	MicroBlaze General Notes	Core presets, max frequencies, multi-core TMR pattern
1	MicroBlaze GPIO	Vivado block design flow, XSA export, Vitis platform + app project setup

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Vivado Toolflow

#	Topic	Key Concept
0	Vivado Troubleshooting Log	Running log of Vivado issues and fixes
1	Programming FPGA with Quad SPI Flash	Bitstream compression, QSPI flash programming workflow

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DSP

#	Project	Key Concept
0	dsp00_dds_from_scratch — coming soon	Phase accumulator, ROM LUT, frequency resolution

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References & Acknowledgements

This repository draws on Xilinx/AMD documentation, HDL textbooks, YouTube tutorials, and community resources. Original sources are cited within each subproject's README.