ASIC design flow implementation for digital circuits, RTL simulation to physical design using Cadence tools.
SystemVerilog ASIC Portfolio: RISC-V SoC Integration, UVM Verification, AI Accelerators & DSP. Full Flow from RTL to GDSII (Cadence).
Layered SystemVerilog testbench for verifying a parameterized Synchronous FIFO. Includes directed and constrained-random tests, functional coverage, assertions, and scoreboard-based checking.
This project presents the verification of a FIFO design using the UVM.
Exercícios desenvolvidos durante a disciplina Concepção Estruturada de Circuitos Integrados, relacionando os mais diversos assuntos da mesma.
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