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soc: microchip: Introduce pic32cxsg sg41 #86952

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soc: microchip: Introduce pic32cxsg sg41 #86952

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2218375
modules: microchip Addition of pic32cxsg modules
MyGh64605 Mar 11, 2025
a151edd
dts: arm: microchip Addition of pic32cxsg
MyGh64605 Mar 11, 2025
7adc77c
soc: microchip: pic32cxsg Addition of pic32cxsg
MyGh64605 Mar 11, 2025
74b0f44
dts: pinctl: Add pinctrl node to PIC32CXSG dtsi
MyGh64605 Aug 4, 2025
2f35e49
drivers: pinctrl Addition of pic32cxsg pin control
MyGh64605 Mar 11, 2025
750923e
dts: serial: Use pic32cxsg compatiable for sercom
MyGh64605 Aug 4, 2025
9608226
drivers: serial: microchip Addition of pic32cxsg serial
MyGh64605 Mar 11, 2025
daa9f91
boards: microchip Addition of pic32cxsg board
MyGh64605 Mar 11, 2025
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22 changes: 22 additions & 0 deletions dts/arm/microchip/pic32c/pic32cx_sg/pic32cx1025sg.dtsi
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Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
/*
* Copyright (c) 2024 Microchip
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <mem.h>
#include <microchip/pic32c/pic32cx_sg/pic32cxsg.dtsi>

/ {
soc {
nvmctrl@41004000 {
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Order by memory address. This is the devicetree standard we use.
Review all to make sure we did not missed any.

flash0: flash@0 {
reg = <0x0 DT_SIZE_K(1024)>;
};
};

sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(256)>;
};
};
};
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