soc: microchip: Introduce pic32cxsg sg41 #86952

MyGh64605 · 2025-03-11T18:00:52Z

Commits for pic32cxsg SG41 Curiosity Ultra board, 'Hello World' basics, arm, pinctrl, serial, board

nordicjm · 2025-03-12T10:08:43Z

dts/arm/microchip/pic32cxsg.dtsi

+
+		id: device_id@8061fc {
+			compatible = "atmel,sam0-id";
+			reg =	<0x008061FC 0x4>,


double space after equals

not addressed

dts/arm/microchip/pic32cxsg.dtsi

nordicjm · 2025-03-12T10:10:13Z

soc/microchip/pic32cxsg/Kconfig

+# Microchip PIC32CXSG MCU family configuration options
+
+# Copyright (c) 2024 Microchip
+# SPDX-License-Identifier: Apache-2.0


Suggested change

# Microchip PIC32CXSG MCU family configuration options

# Copyright (c) 2024 Microchip

# SPDX-License-Identifier: Apache-2.0

# Microchip PIC32CXSG MCU family configuration options

# Copyright (c) 2024 Microchip

# SPDX-License-Identifier: Apache-2.0

having all headers the same would be nice

soc/microchip/pic32cxsg/Kconfig.defconfig

soc/microchip/pic32cxsg/common/Kconfig.pic32cxsg

nordicjm · 2025-03-12T10:13:37Z

soc/microchip/pic32cxsg/common/bossa.c

+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+


this file already exists, move the existing file to a common place and include it

what could be a common place for 2 different vendors?

atmel is microchip so it can be microchip, or maybe even soc/common

nordicjm · 2025-03-12T10:15:52Z

drivers/serial/Kconfig.pic32cxsg

+	  This option enables the SERCOMx USART driver for Microchip PIC32CXSG MCUs.
+
+config UART_PIC32CXSG_ASYNC
+	bool "Async UART support for Microchip PIC32CXSG series."


Suggested change

bool "Async UART support for Microchip PIC32CXSG series."

bool "Async UART support for Microchip PIC32CXSG series"

nordicjm · 2025-03-12T10:16:39Z

boards/microchip/pic32cxsg41_cult/doc/img/PIC32CXSG41-pinout1.jpg

all images -> webp then use https://tinypng.com/

not addressed

nordicjm · 2025-03-12T10:16:56Z

boards/microchip/pic32cxsg41_cult/doc/index.rst

+Supported Features
+==================
+
+The pic32cxsg41_cult board configuration supports the following hardware


Suggested change

The pic32cxsg41_cult board configuration supports the following hardware

The ``pic32cxsg41_cult`` board supports the following hardware

boards/microchip/pic32cxsg41_cult/pic32cxsg41_cult.dts

MyGh64605 · 2025-04-15T17:59:36Z

@nandojve @nordicjm Completed compliance checks

nordicjm

fix raised issues

MyGh64605 · 2025-04-16T13:47:09Z

@nordicjm please clarify your issues pertaining to:

```
  pinmux_c: pinmux@41008100 {
```
```
  	compatible = "atmel,sam0-pinmux";
```
```
  	reg = <0x41008100 0x80>;
```
```
  };
```
```
  pinmux_d: pinmux@41008180 {
```
```
  	compatible = "atmel,sam0-pinmux";
```
```
  	reg = <0x41008180 0x80>;
```
```
  };
```
```
  wdog: watchdog@40002000 {
```
```
  	compatible = "atmel,sam0-watchdog";
```
```
  	reg = <0x40002000 13>;
```
```
  	interrupts = <10 0>;
```
```
  };
```

Note. this file was fixed as follows:
wdog: watchdog@40002000 {
compatible = "atmel,sam0-watchdog";
reg = <0x40002000 13>;
interrupts = <10 0>;
status = "disabled";
};
I cannot disable the 'pinmux's since they are integral to 'pinctrl' i.e. peripheral mux selection

};

soc {
```
  sram0: memory@20000000 {
```
```
  	compatible = "mmio-sram";
```
```
  	reg = <0x20000000 0x40000>;
```
```
  };
```
```
  backup0: memory@47000000 {
```
```
  	compatible = "mmio-sram";
```
```
  	reg = <0x47000000 0x2000>;
```
```
  };
```
```
  id: device_id@8061fc {
```
```
  	compatible = "atmel,sam0-id";
```
```
  	reg =	<0x008061FC 0x4>,
```

not addressed

Thank you.

nordicjm · 2025-04-17T07:14:25Z

5856d44#diff-7862f1c4371a54c6987f57ec439dff007b41c783916fd8a9fa40dab8b6ea433eR84

double space after equals, original comment raised, not fixed comment raised, still not fixed

5856d44#diff-7862f1c4371a54c6987f57ec439dff007b41c783916fd8a9fa40dab8b6ea433eR170

nodes should be disabled in files in dts folder then enabled by the board, nodes that do not have status = "disabled"; will be enabled, original comment raised, not fixed comment raised, still not fixed

4ecdf64#diff-b4bd73e4a70f8a965919730caf1e466cef1f54de68132c629187f352e1562506R16

Missing newline, between elements, original comment raised, still not fixed

etc.

MyGh64605 · 2025-04-17T18:10:11Z

@nandojve @nordicjm @scottwcpg @TheSilverBB

We force pushed more changes on 04/15/2025, Zephyr ran validation tests afterwards.
We made some more changes due to these checks but cannot push due to conflicts. We noticed that the PR branch did not update, nor did our 'microchiptech' branch. we are wondering why the changes were not accepted, is it because draft PRs are handled differently?

kartben · 2025-04-17T19:41:47Z

We made some more changes due to these checks but cannot push due to conflicts.

You need to resolve the conflicts and force push again. Please share more details if you still experience issues

MyGh64605 · 2025-04-25T19:24:10Z

@nandojve @scottwcpg @nordicjm @TheSilverBB
Since the original PR was submitted from a windows repo and the changes were submitted from a WSL repo. We believe it is best that we cancel this PR and then we will create a new.
Any objections or suggestions ?

kartben · 2025-04-25T19:33:42Z

I don't think there should be anything special about a "windows" or a "WSL" repo. Just sync / force push the changes you made to this PR's branch?
Creating a new PR should really be avoided as history of reviews/discussions would be lost.

scottwcpg · 2025-04-25T19:59:37Z

@kartben
Hi. I have been help the PR author. We observed force pushing changes up triggers CI but the files are not being updated with the local changes. The WSL setup was created by creating the same branch name not by pulling down the PR. This may be why it does not update the files. Should the PR author save off local files, delete the local branch, pull down the PR, rebase applying the local changes, then force push? Would this re-sync local and the PR?

MyGh64605 · 2025-04-29T20:45:06Z

@nandojve
Are the tests run on each individual commit ?
We tried your command. "git push -f --set-upstream origin pic32cxsg_helloworld"
And all of our files reverted back to before our changes, even locally.

We want to kill this PR and start over, using WSL.

If we separate into different PRs, would this help ?

We add soc, dts, etc..
The last PR would be 'boards' .
At that time would all the compliance tests be executed ?
Or do the tests run on each PR ?

nandojve · 2025-04-30T20:10:41Z

Hi @MyGh64605 ,

@nandojve Are the tests run on each individual commit ?
No, they only run on top of latest commit.

We tried your command. "git push -f --set-upstream origin pic32cxsg_helloworld" And all of our files reverted back to before our changes, even locally.

We want to kill this PR and start over, using WSL.

If we separate into different PRs, would this help ?

My afraid is that if you close this and open another PR that will be the 4th attempt. This means that mostly on each changes that we request you open a new PR and we lost all the history. In my impression, the way you are managing the git workflow is not OK. I work with people everyday and I don't this kind of problems. for example, you could copy the content from the problematic machine and transfer to another one to send the new content.

git is a very reliable tool and if you know it well you know that content don't vanish. Try to check your git reflog for instance.

We add soc, dts, etc.. The last PR would be 'boards' . At that time would all the compliance tests be executed ? Or do the tests run on each PR ?

I believe that documentation is clear about this and we should only bring content that can be build. At moment, the most painful job in Zephyr is bring a new SoC. It is really exhausting and I'm not the only one that think that this should be changed to allow somehow easy adoption.

On my perspective the content that is on this PR is the minimum to introduce the platform in a way that you can use it. What is necessary is figure out how you can review the request in 24h and send the updates ASAP.

In regards to close this PR and open a new one I'll abstain myself and let that to @nordicjm and @kartben to decide.

nordicjm · 2025-05-09T11:16:20Z

In regards to close this PR and open a new one I'll abstain myself and let that to @nordicjm and @kartben to decide.

Yeah please just fix the pr as-is, don't care how you do it on your choice of OS but millions of people use github and are able to submit PRs so fix your environment and update the PR but do not close this and open a duplicate PR, that's not helpful to anyone

MyGh64605 · 2025-05-21T17:58:40Z

@nandojve @scottwcpg @nordicjm @TheSilverBB
We have successfully passed all checks.
Please review and let us know the next step(s).
When can we press the 'Ready for review' button ?

nordicjm · 2025-05-22T05:47:04Z

@nandojve @scottwcpg @nordicjm @TheSilverBB We have successfully passed all checks. Please review and let us know the next step(s). When can we press the 'Ready for review' button ?

Can press that button whenever you feel it is ready to review, it will then ping people asking to review

TheSilverBB · 2025-08-01T18:20:24Z

This PR is still not anywhere near ready, the soc part is a mess of mismatches values and referencing things that don't even exist, other comments have still not been fixed 2 months on. Raised issues need to be fixed, this PR has wasted so much of my time coming back and re-reviewing it only to see that previously raised issues are still present, it takes time out of my day to review things which could be spent on other reviews

@nordicjm Thank you very much for all your time in reviewing this PR. We feel the same pain as you.

We believe all raised issues are now addressed.

@nandojve @kartben @NhMchp @parthitce

nandojve · 2025-08-01T19:03:38Z

Hi Michael ,

Please, reorder the commit in the following order:

manifest: update west.yml for snakecase changes
modules: microchip Addition of pic32cxsg modules
dts: arm: microchip Addition of pic32cxsg
soc: microchip: pic32cxsg Addition of pic32cxsg
drivers: pinctrl Addition of pic32cxsg pin control
drivers: serial: microchip Addition of pic32cxsg serial
boards: microchip Addition of pic32cxsg board

After reorder, you should extract DTS information from commits with other content. This will result in more commits as below:

manifest: update west.yml for snakecase changes
modules: microchip Addition of pic32cxsg modules
dts: arm: microchip Addition of pic32cxsg
soc: microchip: pic32cxsg Addition of pic32cxsg
dts: pinctrl: xxx
drivers: pinctrl Addition of pic32cxsg pin control
dts: serial: xxx
drivers: serial: microchip Addition of pic32cxsg serial
boards: microchip Addition of pic32cxsg board

In the dts: arm: microchip Addition of pic32cxsg you will reduce to the minimal, see 2cc4cb6 if you have any doubt.
In the dts: pinctrl: xxx and dts: serial: xxx you will add all the information related, see 0088612

Make sure that all devicetree nodes are ordered by address, not name.

robertperkel · 2025-08-01T21:12:00Z

Can you add an alias for one of the built-in LEDs? Currently blinky does not build for this board

TheSilverBB · 2025-08-01T22:15:52Z

@robertperkel

Can you add an alias for one of the built-in LEDs? Currently blinky does not build for this board

Short Answer: No.

Long Answer: Later.
When a new soc is added, after the vendor hal is merged, a board PR is created which must support the Hello World project, and only peripherals required to support the Hello World project are included.
Once the board PR for Hello World is merged, then PRs for each remaining peripheral drivers are created and merged and verified on the board.
Blinky uses GPIOs as a peripheral, which will be added after this PR is merged.
Blinky will build for this board after the GPIO driver is added.
PWM Blinky will build after the PWM driver is added.

@nandojve @NhMchp

TheSilverBB · 2025-08-06T04:05:14Z

@nandojve @kartben @NhMchp @parthitce @nordicjm
Is this PR ready to merge?
Is it ok to change the west.yml commit from “revision: pull/34/head” to the latest hal_microchip hash now?
Thanks.

parthitce · 2025-08-06T04:15:43Z

@nandojve @kartben @NhMchp @parthitce @nordicjm Is this PR ready to merge? Is it ok to change the west.yml commit from “revision: pull/34/head” to the latest hal_microchip hash now? Thanks.

If the HAL changes / PR is already merged, please update the manifest and rebase this PR. This will help the CI pass fully.

Addition of pic32cxsg modules Kconfig Signed-off-by: Michael D Sherwood <[email protected]>

Addition of pic32cxsg 'dtsi' files Signed-off-by: Michael D Sherwood <[email protected]>

scottwcpg · 2025-08-07T14:47:21Z

@parthitce @nandojve @TheSilverBB
The original author of the PR, Michael has retired. I was asked to do the final update.
The PR has been rebased to upstream which pulled in an updated west.yaml pointing to a fix for cmsis_6 and Michael's last fix for this PR.

TheSilverBB · 2025-08-07T21:27:59Z

@nandojve @NhMchp The HAL hash code has been updated. Please press the Resolve Conflicts button.
@scottwcpg

soc/microchip/pic32cxsg/common/Kconfig.pic32cxsg

nordicjm · 2025-08-08T07:19:30Z

soc/microchip/pic32cxsg/common/Kconfig.pic32cxsg

+	bool "The external 32 kHz crystal oscillator"
+	depends on DT_HAS_ATMEL_SAM0_OSC32KCTRL_ENABLED
+	help
+	  Say y to enable the external 32 kHZ crystal oscillator at
+	  startup. This can then be selected as the main clock source
+	  for the SOC.


why does this need to be a Kconfig if the crystal is enabled or disabled in devicetree? If the node is there and has status okay that that means it's present and should be used

@nordicjm Your request has been incorporated, Please mark as Resolved. Thanks.

@nordicjm Updated Kconfig.pic32cxsg and removed the ones you pointed out. The remaining setting is set to y if osc32kctrl DT node is enabled.

jfischer-no · 2025-08-11T14:04:14Z

soc/microchip/pic32cxsg/pic32cxsg60/soc.h

+#define TCC3             (0x42001000) /**< \brief (TCC3) APB Base Address */
+#define TCC4             (0x43001000) /**< \brief (TCC4) APB Base Address */
+#define TRNG             (0x42002800) /**< \brief (TRNG) APB Base Address */
+#define USB              (0x41000000) /**< \brief (USB) APB Base Address */


I cannot imagine the use case for these defines. That is what DT_INST_REG_ADDR(n) is for in the drivers. There is no way the soc.h could have something like #define USB.

By the way, the Doxygen comments in soc.h are absolutely pointless.

This probably comes from the DFP pack for the device. These macros are intended for compatibility with other compiler toolchains outside of Zephyr.

The way I understand it, the direction going forward is to keep the DFP packs as unedited in Zephyr as possible, so it is easy to upgrade them, but to store them into the hal project, rather than mainline. Perhaps the DFP files should be placed there, and soc.h should only include the appropriate header? Here's a snippet of my WIP soc.h, for reference:

#if defined(CONFIG_SOC_PIC32CM5112GC00100) #define __PIC32CM5112GC00100__ #elif defined(CONFIG_SOC_PIC32CM5112GC00064) #define __PIC32CM5112GC00064__ #elif defined(CONFIG_SOC_PIC32CM5112GC00048) #define __PIC32CM5112GC00048__ #else #error Device not supported #endif #include <pic32c.h>

(Inside pic32c.h, the DFP macros grab the correct includes / definitions for the specific device)

@jfischer-no I removed all the defines except two: MCLK and GCLK which are required by the Atmel SAM0 UART driver. MCLK and GCLK get their values using DT_REG_ADDR().

Addition of pic32cxsg current family of devices Signed-off-by: Michael D Sherwood <[email protected]>

Added pinctrl node to PIC32CXSG dtsi without driver compatible Signed-off-by: Michael Sherwood <[email protected]>

Addition of pic32cxsg pin control including yaml, bindings, Kconfig, Signed-off-by: Michael D Sherwood <[email protected]>

Use microchip pic32cxsg compatiable for sercom Signed-off-by: Michael Sherwood <[email protected]>

Addition of pic32cxsg serial driver, Kconfig, yaml Signed-off-by: Michael D Sherwood <[email protected]>

Addition of pic32cxsg SG41 Curiosity Ultra board Signed-off-by: Michael D Sherwood <[email protected]>

sonarqubecloud · 2025-08-14T20:26:30Z

Quality Gate passed

Issues
0 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
41.7% Duplication on New Code

See analysis details on SonarQube Cloud

nordicjm · 2025-08-15T07:31:56Z

modules/Kconfig.microchip

+config HAS_PIC32C_HAL
+	bool "Microchip PIC32C HAL drivers support"


where is this used? And why does it have a prompt?

nordicjm · 2025-08-15T07:32:01Z

modules/Kconfig.microchip

+config HAS_PIC32CXSG_HAL
+	bool "Microchip PIC32CXSG HAL drivers support"
+	select HAS_CMSIS_CORE
+	depends on SOC_FAMILY_MICROCHIP_PIC32CXSG


where is this used? And why does it have a prompt?

soc/board files OK

nandojve · 2025-08-15T09:39:33Z

soc/microchip/pic32cxsg/Kconfig

+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_MICROCHIP_PIC32CXSG
+	select PIC32C


@MyGh64605 ,

It seems that you want select options to your HAL based in the family. Why not just select all this options in the module itself, something like:

config PIC32C bool select HAS_CMSIS_CORE config HAS_PIC32C_HAL bool select PIC32C config HAS_PIC32CXSG_HAL bool select HAS_PIC32C_HAL

nandojve · 2025-08-15T09:47:23Z

soc/microchip/pic32cxsg/Kconfig

+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_MICROCHIP_PIC32CXSG
+	select PIC32C


What you want is define all the HAL at once. This can be achieved by

- select PIC32C + select HAS_PIC32CXSG_HAL

nandojve · 2025-08-15T09:49:39Z

dts/arm/microchip/pic32c/pic32cx_sg/pic32cx1025sg.dtsi

+
+/ {
+	soc {
+		nvmctrl@41004000 {


Order by memory address. This is the devicetree standard we use.
Review all to make sure we did not missed any.

nandojve · 2025-08-15T09:57:43Z

soc/microchip/pic32cxsg/common/Kconfig.pic32cxsg

+
+if SOC_FAMILY_MICROCHIP_PIC32CXSG
+
+config SOC_MICROCHIP_PIC32CXSG_XOSC32K


Since it is on devicetree, this config is useless and must be dropped.

nandojve · 2025-08-15T09:58:38Z

soc/microchip/pic32cxsg/common/microchip_pic32cxsg_dt.h

@@ -0,0 +1,404 @@
+/*
+ * Copyright (c) 2024 Microchip


If you copy and rename, you should keep original copyrights.
Add original copyrights.

nandojve · 2025-08-15T10:16:57Z

dts/bindings/serial/microchip,pic32cxsg-uart.yaml

+# Copyright (c) 2024 Microchip
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip PIC32CXSG SERCOM UART driver


this is the devicetree binding, should be in the previous commit.

nandojve · 2025-08-15T10:19:18Z

drivers/serial/CMakeLists.txt

@@ -64,6 +64,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_NUMICRO uart_numicro.c)
 zephyr_library_sources_ifdef(CONFIG_UART_NXP_S32_LINFLEXD uart_nxp_s32_linflexd.c)
 zephyr_library_sources_ifdef(CONFIG_UART_OPENTITAN uart_opentitan.c)
 zephyr_library_sources_ifdef(CONFIG_UART_PDL_INFINEON_CAT1 uart_ifx_cat1_pdl.c)
+zephyr_library_sources_ifdef(CONFIG_UART_PIC32CXSG uart_sam0.c)


This driver support only one binding at moment.

zephyr/drivers/serial/uart_sam0.c

Line 8 in aa6f87d

#define DT_DRV_COMPAT atmel_sam0_uart

nandojve · 2025-08-15T10:21:33Z

boards/microchip/pic32cxsg41_cult/pic32cxsg41_cult.dts

+&tcc0 {
+	compatible = "atmel,sam0-tcc-pwm";
+
+	/* Gives a maximum period of 1.1s for 120MHz main clock */
+
+	prescaler = <8>;
+
+	#pwm-cells = <2>;
+
+	pinctrl-0 = <&pwm_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};


The only drivers that should be available are pinctrl and serial. Drop all others.

nandojve · 2025-08-15T10:23:26Z

soc/microchip/pic32cxsg/common/CMakeLists.txt

+
+zephyr_sources(soc_port.c)
+
+zephyr_sources_ifdef(CONFIG_BOOTLOADER_BOSSA bossa.c)


This should be dropped for now. When you add on a board (another PR) you can add here.

nandojve · 2025-08-15T10:33:33Z

boards/microchip/pic32cxsg41_cult/Kconfig.defconfig

+# Copyright (c) 2024 Microchip
+# SPDX-License-Identifier: Apache-2.0
+
+if ETH_SAM_GMAC


This is not essential.

scottwcpg requested a review from nandojve March 11, 2025 18:01

nandojve self-assigned this Mar 11, 2025

nordicjm reviewed Mar 12, 2025

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MyGh64605 force-pushed the pic32cxsg_helloworld branch from fb11141 to 7ff07ad Compare April 15, 2025 17:41

nordicjm requested changes Apr 16, 2025

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MyGh64605 force-pushed the pic32cxsg_helloworld branch from 7ff07ad to 138a957 Compare April 29, 2025 18:57

nandojve requested a review from nordicjm April 29, 2025 19:39

MyGh64605 force-pushed the pic32cxsg_helloworld branch 2 times, most recently from 92df3a3 to c22e022 Compare May 21, 2025 17:19

MyGh64605 marked this pull request as ready for review May 22, 2025 12:57

github-actions bot added area: HWINFO Hardware Information Driver platform: Microchip SAM Microchip SAM Platform (formerly Atmel SAM) area: Pinctrl platform: Microchip MEC Microchip MEC Platform area: UART Universal Asynchronous Receiver-Transmitter labels May 22, 2025

github-actions bot requested review from albertofloyd and alexanderwachter May 22, 2025 12:58

nandojve changed the title ~~Pic32cxsg helloworld - commits for pic32cxsg SG41~~ soc: microchip: Introduce pic32cxsg sg41 Aug 1, 2025

MyGh64605 force-pushed the pic32cxsg_helloworld branch from e0da164 to 455db95 Compare August 4, 2025 15:56

MyGh64605 added 2 commits August 7, 2025 09:59

modules: microchip Addition of pic32cxsg modules

2218375

Addition of pic32cxsg modules Kconfig Signed-off-by: Michael D Sherwood <[email protected]>

dts: arm: microchip Addition of pic32cxsg

a151edd

Addition of pic32cxsg 'dtsi' files Signed-off-by: Michael D Sherwood <[email protected]>

scottwcpg force-pushed the pic32cxsg_helloworld branch from 455db95 to e6b42ca Compare August 7, 2025 14:44

github-actions bot removed manifest manifest-hal_microchip DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Aug 7, 2025

nordicjm reviewed Aug 8, 2025

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soc/microchip/pic32cxsg/common/Kconfig.pic32cxsg Outdated Show resolved Hide resolved

nordicjm reviewed Aug 8, 2025

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jfischer-no requested changes Aug 11, 2025

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MyGh64605 added 6 commits August 12, 2025 15:50

soc: microchip: pic32cxsg Addition of pic32cxsg

7adc77c

Addition of pic32cxsg current family of devices Signed-off-by: Michael D Sherwood <[email protected]>

dts: pinctl: Add pinctrl node to PIC32CXSG dtsi

74b0f44

Added pinctrl node to PIC32CXSG dtsi without driver compatible Signed-off-by: Michael Sherwood <[email protected]>

drivers: pinctrl Addition of pic32cxsg pin control

2f35e49

Addition of pic32cxsg pin control including yaml, bindings, Kconfig, Signed-off-by: Michael D Sherwood <[email protected]>

dts: serial: Use pic32cxsg compatiable for sercom

750923e

Use microchip pic32cxsg compatiable for sercom Signed-off-by: Michael Sherwood <[email protected]>

drivers: serial: microchip Addition of pic32cxsg serial

9608226

Addition of pic32cxsg serial driver, Kconfig, yaml Signed-off-by: Michael D Sherwood <[email protected]>

boards: microchip Addition of pic32cxsg board

daa9f91

Addition of pic32cxsg SG41 Curiosity Ultra board Signed-off-by: Michael D Sherwood <[email protected]>

scottwcpg force-pushed the pic32cxsg_helloworld branch from e6b42ca to daa9f91 Compare August 14, 2025 20:09

nordicjm reviewed Aug 15, 2025

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nandojve requested changes Aug 15, 2025

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	bool "Async UART support for Microchip PIC32CXSG series."
	bool "Async UART support for Microchip PIC32CXSG series"

	The pic32cxsg41_cult board configuration supports the following hardware
	The ``pic32cxsg41_cult`` board supports the following hardware

		config HAS_PIC32C_HAL
		bool "Microchip PIC32C HAL drivers support"


		if SOC_FAMILY_MICROCHIP_PIC32CXSG

		config SOC_MICROCHIP_PIC32CXSG_XOSC32K


		zephyr_sources(soc_port.c)

		zephyr_sources_ifdef(CONFIG_BOOTLOADER_BOSSA bossa.c)

soc: microchip: Introduce pic32cxsg sg41 #86952

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soc: microchip: Introduce pic32cxsg sg41 #86952

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