soc: microchip: Introduce pic32cxsg sg41

drivers/serial/CMakeLists.txt

@@ -64,6 +64,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_NUMICRO uart_numicro.c)
 zephyr_library_sources_ifdef(CONFIG_UART_NXP_S32_LINFLEXD uart_nxp_s32_linflexd.c)
 zephyr_library_sources_ifdef(CONFIG_UART_OPENTITAN uart_opentitan.c)
 zephyr_library_sources_ifdef(CONFIG_UART_PDL_INFINEON_CAT1 uart_ifx_cat1_pdl.c)
+zephyr_library_sources_ifdef(CONFIG_UART_PIC32CXSG uart_sam0.c)
 zephyr_library_sources_ifdef(CONFIG_UART_PIPE uart_pipe.c)
 zephyr_library_sources_ifdef(CONFIG_UART_PL011 uart_pl011.c)
 zephyr_library_sources_ifdef(CONFIG_UART_PSOC6 uart_psoc6.c)

drivers/serial/Kconfig

@@ -207,6 +207,7 @@ rsource "Kconfig.numaker"
 rsource "Kconfig.numicro"
 rsource "Kconfig.nxp_s32"
 rsource "Kconfig.opentitan"
+rsource "Kconfig.pic32cxsg"
 rsource "Kconfig.pl011"
 rsource "Kconfig.psoc6"
 rsource "Kconfig.ql_usbserialport_s3b"

drivers/serial/Kconfig.pic32cxsg

@@ -0,0 +1,18 @@
+# Microchip PIC32CXSG SERCOM configuration options
+
+# Copyright (c) 2024 Microchip
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_PIC32CXSG
+	bool "Microchip PIC32CXSG series SERCOM USART driver"
+	default y
+	depends on DT_HAS_MICROCHIP_PIC32CXSG_UART_ENABLED
+	select SERIAL_HAS_DRIVER
+	select SERIAL_SUPPORT_INTERRUPT
+	help
+	  This option enables the SERCOMx USART driver for Microchip PIC32CXSG MCUs.
+
+config UART_PIC32CXSG_ASYNC
+	bool "Async UART support for Microchip PIC32CXSG series"
+	depends on UART_PIC32CXSG
+	depends on UART_ASYNC_API

dts/bindings/arm/microchip,pic32cxsg-sercom.yaml

@@ -0,0 +1,17 @@
+description: Microchip PIC32CXSG multi-protocol (UART, SPI, I2C) SERCOM unit
+
+compatible: "microchip,pic32cxsg-sercom"
+
+include:
+  - name: base.yaml
+  - name: atmel,assigned-clocks.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clocks:
+    required: true

dts/bindings/serial/microchip,pic32cxsg-uart.yaml

@@ -0,0 +1,93 @@
+# Copyright (c) 2024 Microchip
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip PIC32CXSG SERCOM UART driver
+
+compatible: "microchip,pic32cxsg-uart"
+
+include:
+  - name: uart-controller.yaml
+  - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clocks:
+    required: true
+
+  clock-names:
+    required: true
+
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
+    required: true
+
+  rxpo:
+    type: int
+    required: true
+    description: |
+      Receive Data Pinout. An enumeration with the following values:
+
+      +-------+---------------+
+      | Value | RX Pin        |
+      +-------+---------------+
+      |     0 | SERCOM_PAD[0] |
+      +-------+---------------+
+      |     1 | SERCOM_PAD[1] |
+      +-------+---------------+
+      |     2 | SERCOM_PAD[2] |
+      +-------+---------------+
+      |     3 | SERCOM_PAD[3] |
+      +-------+---------------+
+
+
+  txpo:
+    type: int
+    required: true
+    description: |
+      Transmit Data Pinout. An enumeration with values that depend on the
+      hardware being used. This controls both the transmit pins and if
+      hardware flow control is used.
+
+      PIC32CXSG:
+
+      +-------+---------------+---------------+---------------+
+      | Value | TX Pin        | RTS           | CTS           |
+      +-------+---------------+---------------+---------------+
+      |     0 | SERCOM_PAD[0] |           N/A |           N/A |
+      +-------+---------------+---------------+---------------+
+      |     1 | Reserved                                      |
+      +-------+---------------+---------------+---------------+
+      |     2 | SERCOM_PAD[0] | SERCOM_PAD[2] | SERCOM_PAD[3] |
+      +-------+---------------+---------------+---------------+
+      |     3 | SERCOM_PAD[0] | SERCOM_PAD[2] |           N/A |
+      +-------+---------------+---------------+---------------+
+
+
+  collision-detection:
+    type: boolean
+    description: Enable collision detection for half-duplex mode.
+
+  dmas:
+    description: |
+      Optional TX & RX dma specifiers.  Each specifier will have a phandle
+      reference to the dmac controller, the channel number, and peripheral
+      trigger source.
+
+      For example dmas for TX, RX on SERCOM3
+         dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
+
+  dma-names:
+    description: |
+      Required if the dmas property exists.  This should be "tx" and "rx"
+      to match the dmas property.
+
+      For example
+         dma-names = "tx", "rx";