drivers: dma: sam: add support for sama7g5 DMA Controller (XDMAC) #92816
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Please review the channel state machine diagram. It's one of the very few requirements I have for DMA drivers, to follow the expected results for applying channel changes.
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@teburd |
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Hi @TonyHan11 , Reorder the commits. |
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Reordered with adding the dts first, thanks. |
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Add dma nodes to sama7g5.dtsi file. Signed-off-by: Tony Han <[email protected]>
Enable cache manamegent for sama7g5 series. Signed-off-by: Tony Han <[email protected]>
When the XDMAC is activated in the DT, configure it's register region with strong ordered, read and write access. Signed-off-by: Tony Han <[email protected]>
This update xdmac driver to support multiple DMA instancess. Signed-off-by: Tony Han <[email protected]>
As the number of DMA channels could be different between DMA instances, get the number from "XDMAC Global Type Register" and validate the channel used. Signed-off-by: Tony Han <[email protected]>
Update the driver to support sama7g5 XDMAC peripheral. Signed-off-by: Tony Han <[email protected]>
Add support for XDMA channel read write suspend and read write resume. Signed-off-by: Tony Han <[email protected]>
Add state machine for config/start/stop/resume/suspend for DMA channels. Signed-off-by: Tony Han <[email protected]>
Add DMA nodes to sama7g54_ek.dts files. Add DMA to sama7g54_ek.yaml support list. Signed-off-by: Tony Han <[email protected]>
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| - zephyr | ||
| ram: 128 | ||
| supported: | ||
| - dma |
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Check the tests to make sure board fulfill requirements to run the tests.
For instance
INFO - 22/1005 sama7g54_ek/sama7g54 drivers.dma.loop_transfer FILTERED (runtime filter)
Review all tests and some samples that uses DMA.
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tests/drivers/dma/chan_blen_transfer and tests/drivers/dma/loop_transfer test failed due to cache coherency is not handled by the tests (if cache is disabled it's OK). According to https://docs.zephyrproject.org/latest/hardware/peripherals/dma.html, the DMA drivers in general do not handle cache coherency.
Changes in this PR includes: