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12 changes: 12 additions & 0 deletions boards/microchip/sam/sama7g54_ek/sama7g54_ek.dts
Original file line number Diff line number Diff line change
Expand Up @@ -37,6 +37,18 @@
};
};

&dma0 {
status = "okay";
};

&dma1 {
status = "okay";
};

&dma2 {
status = "okay";
};

&flx3 {
mchp,flexcom-mode = <SAM_FLEXCOM_MODE_USART>;
status = "okay";
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1 change: 1 addition & 0 deletions boards/microchip/sam/sama7g54_ek/sama7g54_ek.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@ toolchain:
- zephyr
ram: 128
supported:
- dma
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Check the tests to make sure board fulfill requirements to run the tests.
For instance
INFO - 22/1005 sama7g54_ek/sama7g54 drivers.dma.loop_transfer FILTERED (runtime filter)
Review all tests and some samples that uses DMA.

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tests/drivers/dma/chan_blen_transfer and tests/drivers/dma/loop_transfer test failed due to cache coherency is not handled by the tests (if cache is disabled it's OK). According to https://docs.zephyrproject.org/latest/hardware/peripherals/dma.html, the DMA drivers in general do not handle cache coherency.

- shell
- uart
vendor: microchip
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