Add Basic support for Microchip SAM D5X/E5X Family devices

boards/microchip/sam/sam_e54_xpro/Kconfig.sam_e54_xpro

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SAM_E54_XPRO
+	select SOC_ATSAME54P20A

boards/microchip/sam/sam_e54_xpro/board.cmake

@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/microchip/sam/sam_e54_xpro/board.yml

@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+  name: sam_e54_xpro
+  full_name: SAM E54 Xplained Pro
+  vendor: microchip
+  socs:
+    - name: atsame54p20a

boards/microchip/sam/sam_e54_xpro/doc/index.rst

@@ -0,0 +1,94 @@
+.. zephyr:board:: sam_e54_xpro
+
+Overview
+********
+
+The SAM E54 Xplained Pro evaluation kit is ideal for evaluation and
+prototyping with the SAM E54 Cortex®-M4F processor-based
+microcontrollers. The kit includes Microchip’s Embedded Debugger (EDBG),
+which provides a full debug interface without the need for additional
+hardware.
+
+Hardware
+********
+
+- ATSAME54P20A ARM Cortex-M4F processor at 120 MHz
+- 32.768 kHz crystal oscillator
+- 12 MHz crystal oscillator
+- 1024 KiB flash memory and 256 KiB of RAM
+- One yellow user LED
+- One mechanical user push button
+- One reset button
+- On-board USB based EDBG unit with serial console
+- One QTouch® PTC button
+- 32 MiB QSPI Flash
+- ATECC508 CryptoAuthentication™  device
+- AT24MAC402 serial EEPROM with EUI-48™ MAC address
+- Ethernet
+
+   - RJ45 connector with built-in magnetics
+   - KSZ8091RNA PHY
+   - 10Base-T/100Base-TX IEE 802.3 compliant Ethernet transceiver
+
+- USB interface, host, and device
+- SD/SDIO card connector
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+The `SAM E54 Xplained Pro User Guide`_ has detailed information about board connections.
+
+Programming and Debugging
+*************************
+
+The SAM E54 Xplained Pro features an on-board Microchip Embedded Debugger (EDBG),
+which provides both a standard debug interface and a virtual serial port used as the Zephyr console.
+SERCOM2 of the ATSAME54P20A MCU is configured as a USART for console output.
+
+#. Connect the board to your host machine using the debug USB port.
+
+#. Open a terminal and start a serial console on the corresponding port.
+   On Linux, this is typically ``/dev/ttyACM0``. For example:
+
+   .. code-block:: console
+
+      $ minicom -D /dev/ttyACM0 -o
+
+   The -o option tells minicom not to send the modem initialization
+   string. Connection should be configured as follows:
+
+   - Speed: 115200
+   - Data: 8 bits
+   - Parity: None
+   - Stop bits: 1
+
+#. Build and flash the Zephyr ``hello_world`` sample application:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: sam_e54_xpro
+      :goals: flash
+      :compact:
+
+#. Observe output on the terminal. If everything is set up correctly, you should see:
+
+   .. code-block:: console
+
+      Hello World! same_54_xpro
+
+References
+**********
+
+SAM E54 Product Page:
+    https://www.microchip.com/en-us/product/ATSAME54P20A
+
+SAM E54 Xplained Pro evaluation kit Page:
+    https://www.microchip.com/en-us/development-tool/ATSAME54-XPRO
+
+.. _SAM E54 Xplained Pro User Guide:
+    https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/UserGuides/70005321A.pdf

boards/microchip/sam/sam_e54_xpro/sam_e54_xpro-pinctrl.dtsi

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/sam/sam_d5x_e5x/atsame54/atsame54p20a-pinctrl.h>
+
+&pinctrl {
+	sercom2_uart_default: sercom2_uart_default {
+		group1 {
+			pinmux = <PB25D_SERCOM2_PAD0>,
+				 <PB24D_SERCOM2_PAD1>;
+		};
+	};
+};

boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.dts

@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2025 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <microchip/sam/sam_d5x_e5x/atsame54/atsame54p20a.dtsi>
+#include "sam_e54_xpro-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "SAM E54 Xplained Pro";
+	compatible = "same54,xpro", "microchip,atsame54p20a", "microchip,same54";
+
+	chosen {
+		zephyr,console = &sercom2;
+		zephyr,shell-uart = &sercom2;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * The final 16 KiB is reserved for the application.
+		 * Storage partition will be used by FCB/LittleFS/NVS
+		 * if enabled.
+		 */
+		storage_partition: partition@fc000 {
+			label = "storage";
+			reg = <0x000fc000 0x00004000>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <48000000>;
+};
+
+&sercom2 {
+	status = "okay";
+	compatible = "microchip,sercom-g1-uart";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+	stop-bits = "1";
+
+	rxpo = <1>;
+	txpo = <0>;
+
+	pinctrl-0 = <&sercom2_uart_default>;
+	pinctrl-names = "default";
+};

boards/microchip/sam/sam_e54_xpro/sam_e54_xpro.yaml

@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: sam_e54_xpro
+name: SAM E54 Xplained Pro
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+flash: 1024
+ram: 256
+supported:
+  - pinctrl
+  - shell
+  - uart
+vendor: microchip

boards/microchip/sam/sam_e54_xpro/sam_e54_xpro_defconfig

@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_BUILD_OUTPUT_HEX=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y

boards/microchip/sam/sam_e54_xpro/support/openocd.cfg

@@ -0,0 +1,25 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+source [find interface/cmsis-dap.cfg]
+transport select swd
+
+# chip name
+set CHIPNAME same54p20a
+set ENDIAN little
+set CPUTAPID 0x0bc11477
+
+source [find target/atsame5x.cfg]
+
+reset_config none
+cortex_m reset_config sysresetreq
+
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}

drivers/clock_control/CMakeLists.txt

@@ -10,6 +10,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_FIXED_RATE_CLOCK    clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_GD32                clock_control_gd32.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LITEX               clock_control_litex.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_LPC11U6X            clock_control_lpc11u6x.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_SAM_D5X_E5X    clock_control_mchp_sam_d5x_e5x.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCHP_XEC            clock_control_mchp_xec.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_CCM            clock_control_mcux_ccm.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_MCUX_CCM_REV2       clock_control_mcux_ccm_rev2.c)

drivers/clock_control/Kconfig

@@ -114,4 +114,6 @@ source "drivers/clock_control/Kconfig.wch_rcc"
 
 source "drivers/clock_control/Kconfig.it51xxx"
 
+source "drivers/clock_control/Kconfig.mchp"
+
 endif # CLOCK_CONTROL

drivers/clock_control/Kconfig.mchp

@@ -0,0 +1,26 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_MCHP_COMMON
+	bool
+	help
+	  Common options for Microchip clock control drivers.
+
+config CLOCK_CONTROL_MCHP_SAM_D5X_E5X
+	bool "Microchip SAM D5X/E5X clock controller Support"
+	depends on DT_HAS_MICROCHIP_SAM_D5X_E5X_CLOCK_ENABLED
+	default y
+	select CLOCK_CONTROL_MCHP_COMMON
+	help
+	  Enable clock controller driver for Microchip SAM D5X/E5X SoC family.
+
+if CLOCK_CONTROL_MCHP_COMMON
+
+config CLOCK_CONTROL_MCHP_GET_RATE
+	bool "Get clock rate"
+	default y
+	help
+	  Enable support for retrieving the clock rate. This may increase
+	  code size, depending on the depth of clock source hierarchy.
+
+endif # CLOCK_CONTROL_MCHP_COMMON