Addition of PLLSAI on STM32F4/F7 and enabling of LTDC/DSI on STM32F769I-disco board

boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.conf

@@ -0,0 +1,4 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MEMC=y

boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32f769i_disco.overlay

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&sdram1 {
+	/* Frame buffer memory when cached causes screen flickering. */
+	zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)>;
+};
+
+&zephyr_lcd_controller {
+	ext-sdram = <&sdram1>;
+	def-back-color-red = <0>;
+	def-back-color-green = <0>;
+	def-back-color-blue = <0>;
+	status = "okay";
+};
+
+&pllsai {
+	div-m = <25>;
+	mul-n = <384>;
+	div-r = <5>;
+	div-divr = <8>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&zephyr_mipi_dsi {
+	/* DSI HOST dedicated PLL
+	 * F_VCO = CLK_IN / pll-idf * 2 * pll-ndiv
+	 * PHI = F_VCO / 2 / (1 << pll-odf) = lane_byte_clk
+	 *     = 25 MHz / 5 * 2 * 100 / 2 / (1<<0) / 8 = 62.5 MHz
+	 */
+	pll-ndiv = <100>;
+	pll-idf = <5>;
+	pll-odf = <0>;
+
+	vs-active-high;
+	hs-active-high;
+	de-active-high;
+
+	status = "okay";
+};

boards/st/stm32f429i_disc1/stm32f429i_disc1.dts

@@ -122,6 +122,15 @@
 	status = "okay";
 };
 
+&pllsai {
+	div-m = <8>;
+	mul-n = <192>;
+	div-r = <4>;
+	div-divr = <8>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
 &rcc {
 	clocks = <&pll>;
 	clock-frequency = <DT_FREQ_M(168)>;

boards/st/stm32f746g_disco/stm32f746g_disco.dts

@@ -92,6 +92,15 @@
 	status = "okay";
 };
 
+&pllsai {
+	div-m = <25>;
+	mul-n = <384>;
+	div-r = <5>;
+	div-divr = <8>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
 &rcc {
 	clocks = <&pll>;
 	clock-frequency = <DT_FREQ_M(216)>;

boards/st/stm32f7508_dk/stm32f7508_dk.dts

@@ -83,6 +83,15 @@
 	status = "okay";
 };
 
+&pllsai {
+	div-m = <25>;
+	mul-n = <384>;
+	div-r = <5>;
+	div-divr = <8>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
 &rcc {
 	clocks = <&pll>;
 	clock-frequency = <DT_FREQ_M(216)>;

boards/st/stm32f769i_disco/stm32f769i_disco.dts

@@ -10,6 +10,7 @@
 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
 #include "arduino_r3_connector.dtsi"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
 
 / {
 	model = "STMicroelectronics STM32F769I DISCOVERY board";
@@ -72,6 +73,20 @@
 		input = <&ft6202>;
 	};
 
+	dsi_lcd_qsh_030: connector_dsi_lcd {
+		compatible = "st,dsi-lcd-qsh-030";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <4 0 &gpioi 13 0>,	/* LCD_INT */
+			   <39 0 &gpiod 11 0>,	/* SPDIF_I2S */
+			   <40 0 &gpiob 7 0>,	/* I2C4_SDA */
+			   <44 0 &gpiod 12 0>,	/* I2C4_SCL */
+			   <49 0 &gpioj 2 0>,	/* DSI_TE */
+			   <53 0 &gpioi 14 0>,	/* BL_CTRL */
+			   <57 0 &gpioj 15 0>;	/* DSI_RESET */
+	};
+
 	aliases {
 		led0 = &red_led_1;
 		led1 = &green_led_2;
@@ -134,7 +149,7 @@ arduino_serial: &usart6 {};
 	clock-frequency = <I2C_BITRATE_FAST>;
 };
 
-&i2c4 {
+qsh_030_i2c: &i2c4 {
 	pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pb7>;
 	pinctrl-names = "default";
 	status = "okay";
@@ -282,3 +297,7 @@ zephyr_udc0: &usbotg_hs {
 	phys = <&otghs_ulpi_phy>;
 	status = "okay";
 };
+
+/* alias used by display shields */
+zephyr_mipi_dsi: &mipi_dsi {};
+zephyr_lcd_controller: &ltdc {};

drivers/clock_control/clock_stm32_ll_common.c

@@ -228,6 +228,41 @@ int enabled_clock(uint32_t src_clk)
 		}
 		break;
 #endif /* STM32_SRC_PLLI2S_R */
+#if defined(STM32_SRC_PLLSAI_P)
+	case STM32_SRC_PLLSAI_P:
+		if (!IS_ENABLED(STM32_PLLSAI_P_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif /* STM32_SRC_PLLSAI_P */
+#if defined(STM32_SRC_PLLSAI_Q)
+	case STM32_SRC_PLLSAI_Q:
+		if (!IS_ENABLED(STM32_PLLSAI_Q_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif /* STM32_SRC_PLLSAI_Q */
+#if defined(STM32_SRC_PLLSAI_DIVQ)
+	case STM32_SRC_PLLSAI_DIVQ:
+		if (!IS_ENABLED(STM32_PLLSAI_Q_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif /* STM32_SRC_PLLSAI_DIVQ */
+#if defined(STM32_SRC_PLLSAI_R)
+	case STM32_SRC_PLLSAI_R:
+		if (!IS_ENABLED(STM32_PLLSAI_R_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif /* STM32_SRC_PLLSAI_R */
+#if defined(STM32_SRC_PLLSAI_DIVR)
+	case STM32_SRC_PLLSAI_DIVR:
+		if (!IS_ENABLED(STM32_PLLSAI_R_ENABLED)) {
+			r = -ENOTSUP;
+		}
+		break;
+#endif /* STM32_SRC_PLLSAI_DIVR */
 #if defined(STM32_SRC_PLLSAI1_P)
 	case STM32_SRC_PLLSAI1_P:
 		if (!IS_ENABLED(STM32_PLLSAI1_P_ENABLED)) {
@@ -449,104 +484,148 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
 	case STM32_SRC_SYSCLK:
 		*rate = SystemCoreClock * STM32_CORE_PRESCALER;
 		break;
-#if defined(STM32_SRC_PLLCLK) & defined(STM32_SYSCLK_SRC_PLL)
+#if defined(STM32_SRC_PLLCLK) && defined(STM32_SYSCLK_SRC_PLL)
 	case STM32_SRC_PLLCLK:
 		if (get_pllout_frequency() == 0) {
 			return -EIO;
 		}
 		*rate = get_pllout_frequency();
 		break;
 #endif
-#if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED
+#if defined(STM32_SRC_PLL_P) && STM32_PLL_P_ENABLED
 	case STM32_SRC_PLL_P:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLL_M_DIVISOR,
 					      STM32_PLL_N_MULTIPLIER,
 					      STM32_PLL_P_DIVISOR);
 		break;
 #endif
-#if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED
+#if defined(STM32_SRC_PLL_Q) && STM32_PLL_Q_ENABLED
 	case STM32_SRC_PLL_Q:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLL_M_DIVISOR,
 					      STM32_PLL_N_MULTIPLIER,
 					      STM32_PLL_Q_DIVISOR);
 		break;
 #endif
-#if defined(STM32_SRC_PLL_R) & STM32_PLL_R_ENABLED
+#if defined(STM32_SRC_PLL_R) && STM32_PLL_R_ENABLED
 	case STM32_SRC_PLL_R:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLL_M_DIVISOR,
 					      STM32_PLL_N_MULTIPLIER,
 					      STM32_PLL_R_DIVISOR);
 		break;
 #endif
-#if defined(STM32_SRC_PLLI2S_Q) & STM32_PLLI2S_Q_ENABLED & STM32_PLLI2S_ENABLED
+#if defined(STM32_SRC_PLLI2S_Q) && STM32_PLLI2S_Q_ENABLED && STM32_PLLI2S_ENABLED
 	case STM32_SRC_PLLI2S_Q:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLLI2S_M_DIVISOR,
 					      STM32_PLLI2S_N_MULTIPLIER,
 					      STM32_PLLI2S_Q_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLI2S_Q */
-#if defined(STM32_SRC_PLLI2S_R) & STM32_PLLI2S_ENABLED
+#if defined(STM32_SRC_PLLI2S_R) && STM32_PLLI2S_ENABLED
 	case STM32_SRC_PLLI2S_R:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLLI2S_M_DIVISOR,
 					      STM32_PLLI2S_N_MULTIPLIER,
 					      STM32_PLLI2S_R_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLI2S_R */
-#if defined(STM32_SRC_PLLSAI1_P) & STM32_PLLSAI1_P_ENABLED
+#if defined(STM32_SRC_PLLSAI_P) && STM32_PLLSAI_P_ENABLED
+	case STM32_SRC_PLLSAI_P:
+		*rate = get_pll_div_frequency(get_pllsaisrc_frequency(),
+					      STM32_PLLSAI_M_DIVISOR,
+					      STM32_PLLSAI_N_MULTIPLIER,
+					      STM32_PLLSAI_P_DIVISOR);
+		break;
+#endif /* STM32_SRC_PLLSAI_P */
+#if defined(STM32_SRC_PLLSAI_Q) && STM32_PLLSAI_Q_ENABLED
+	case STM32_SRC_PLLSAI_Q:
+		*rate = get_pll_div_frequency(get_pllsaisrc_frequency(),
+					      STM32_PLLSAI_M_DIVISOR,
+					      STM32_PLLSAI_N_MULTIPLIER,
+					      STM32_PLLSAI_Q_DIVISOR);
+		break;
+#endif /* STM32_SRC_PLLSAI_Q */
+#if defined(STM32_SRC_PLLSAI_DIVQ) && STM32_PLLSAI_Q_ENABLED && STM32_PLLSAI_DIVQ_ENABLED && \
+	defined(STM32_PLLSAI_DIVQ_DIVISOR)
+	case STM32_SRC_PLLSAI_DIVQ:
+		*rate = get_pll_div_frequency(get_pllsaisrc_frequency(),
+					      STM32_PLLSAI_M_DIVISOR,
+					      STM32_PLLSAI_N_MULTIPLIER,
+					      STM32_PLLSAI_Q_DIVISOR);
+		*rate /= STM32_PLLSAI_DIVQ_DIVISOR;
+		break;
+#endif /* STM32_SRC_PLLSAI_DIVQ */
+#if defined(STM32_SRC_PLLSAI_R) && STM32_PLLSAI_R_ENABLED
+	case STM32_SRC_PLLSAI_R:
+		*rate = get_pll_div_frequency(get_pllsaisrc_frequency(),
+					      STM32_PLLSAI_M_DIVISOR,
+					      STM32_PLLSAI_N_MULTIPLIER,
+					      STM32_PLLSAI_R_DIVISOR);
+		break;
+#endif /* STM32_SRC_PLLSAI_R */
+#if defined(STM32_SRC_PLLSAI_DIVR) && STM32_PLLSAI_R_ENABLED && STM32_PLLSAI_DIVR_ENABLED && \
+	defined(STM32_PLLSAI_DIVR_DIVISOR)
+	case STM32_SRC_PLLSAI_DIVR:
+		*rate = get_pll_div_frequency(get_pllsaisrc_frequency(),
+					      STM32_PLLSAI_M_DIVISOR,
+					      STM32_PLLSAI_N_MULTIPLIER,
+					      STM32_PLLSAI_R_DIVISOR);
+		*rate /= STM32_PLLSAI_DIVR_DIVISOR;
+		break;
+#endif /* STM32_SRC_PLLSAI_DIVR */
+#if defined(STM32_SRC_PLLSAI1_P) && STM32_PLLSAI1_P_ENABLED
 	case STM32_SRC_PLLSAI1_P:
 		*rate = get_pll_div_frequency(get_pllsai1src_frequency(),
 					      STM32_PLLSAI1_M_DIVISOR,
 					      STM32_PLLSAI1_N_MULTIPLIER,
 					      STM32_PLLSAI1_P_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI1_P */
-#if defined(STM32_SRC_PLLSAI1_Q) & STM32_PLLSAI1_Q_ENABLED
+#if defined(STM32_SRC_PLLSAI1_Q) && STM32_PLLSAI1_Q_ENABLED
 	case STM32_SRC_PLLSAI1_Q:
 		*rate = get_pll_div_frequency(get_pllsai1src_frequency(),
 					      STM32_PLLSAI1_M_DIVISOR,
 					      STM32_PLLSAI1_N_MULTIPLIER,
 					      STM32_PLLSAI1_Q_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI1_Q */
-#if defined(STM32_SRC_PLLSAI1_R) & STM32_PLLSAI1_R_ENABLED
+#if defined(STM32_SRC_PLLSAI1_R) && STM32_PLLSAI1_R_ENABLED
 	case STM32_SRC_PLLSAI1_R:
 		*rate = get_pll_div_frequency(get_pllsai1src_frequency(),
 					      STM32_PLLSAI1_M_DIVISOR,
 					      STM32_PLLSAI1_N_MULTIPLIER,
 					      STM32_PLLSAI1_R_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI1_R */
-#if defined(STM32_SRC_PLLSAI2_P) & STM32_PLLSAI2_P_ENABLED
+#if defined(STM32_SRC_PLLSAI2_P) && STM32_PLLSAI2_P_ENABLED
 	case STM32_SRC_PLLSAI2_P:
 		*rate = get_pll_div_frequency(get_pllsai2src_frequency(),
 					      STM32_PLLSAI2_M_DIVISOR,
 					      STM32_PLLSAI2_N_MULTIPLIER,
 					      STM32_PLLSAI2_P_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI2_P */
-#if defined(STM32_SRC_PLLSAI2_Q) & STM32_PLLSAI2_Q_ENABLED
+#if defined(STM32_SRC_PLLSAI2_Q) && STM32_PLLSAI2_Q_ENABLED
 	case STM32_SRC_PLLSAI2_Q:
 		*rate = get_pll_div_frequency(get_pllsai2src_frequency(),
 					      STM32_PLLSAI2_M_DIVISOR,
 					      STM32_PLLSAI2_N_MULTIPLIER,
 					      STM32_PLLSAI2_Q_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI2_Q */
-#if defined(STM32_SRC_PLLSAI2_R) & STM32_PLLSAI2_R_ENABLED
+#if defined(STM32_SRC_PLLSAI2_R) && STM32_PLLSAI2_R_ENABLED
 	case STM32_SRC_PLLSAI2_R:
 		*rate = get_pll_div_frequency(get_pllsai2src_frequency(),
 					      STM32_PLLSAI2_M_DIVISOR,
 					      STM32_PLLSAI2_N_MULTIPLIER,
 					      STM32_PLLSAI2_R_DIVISOR);
 		break;
 #endif /* STM32_SRC_PLLSAI2_R */
-#if defined(STM32_SRC_PLLSAI2_DIVR) & STM32_PLLSAI2_R_ENABLED & STM32_PLLSAI2_DIVR_ENABLED \
-	& defined(STM32_PLLSAI2_DIVR_DIVISOR)
+#if defined(STM32_SRC_PLLSAI2_DIVR) && STM32_PLLSAI2_R_ENABLED && STM32_PLLSAI2_DIVR_ENABLED && \
+	defined(STM32_PLLSAI2_DIVR_DIVISOR)
 	case STM32_SRC_PLLSAI2_DIVR:
 		*rate = get_pll_div_frequency(get_pllsai2src_frequency(),
 					      STM32_PLLSAI2_M_DIVISOR,
@@ -733,11 +812,11 @@ static void set_up_plls(void)
 
 #if defined(STM32_PLL_ENABLED)
 
-#if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED
+#if defined(STM32_SRC_PLL_P) && STM32_PLL_P_ENABLED
 	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR));
 	RCC_PLLP_ENABLE();
 #endif
-#if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED
+#if defined(STM32_SRC_PLL_Q) && STM32_PLL_Q_ENABLED
 	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR));
 	RCC_PLLQ_ENABLE();
 #endif
@@ -762,6 +841,16 @@ static void set_up_plls(void)
 	}
 #endif /* STM32_PLLI2S_ENABLED */
 
+#if defined(STM32_PLLSAI_ENABLED)
+	config_pllsai();
+
+	/* Enable PLL */
+	LL_RCC_PLLSAI_Enable();
+	while (LL_RCC_PLLSAI_IsReady() != 1U) {
+		/* Wait for PLL ready */
+	}
+#endif /* STM32_PLLSAI_ENABLED */
+
 #if defined(STM32_PLLSAI1_ENABLED)
 	config_pllsai1();